Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64868 )
Change subject: soc/amd/*: Make mtrr decision based on syscfg ......................................................................
soc/amd/*: Make mtrr decision based on syscfg
The syscfg has to option to automatically mark the range between 4G and TOM2, which contains DRAM, as WB. Making it generally not necessary to allocate MTRRs for memory above 4G if no PCI BARs are placed up there.
Change-Id: Ifbacae28e272ab2f39f268ad034354a9c590d035 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/amd/cezanne/cpu.c M src/soc/amd/picasso/cpu.c M src/soc/amd/sabrina/cpu.c M src/soc/amd/stoneyridge/cpu.c 4 files changed, 41 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/64868/1
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 0e4d7c6..1e2611f 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -7,6 +7,7 @@ #include <assert.h> #include <console/console.h> #include <cpu/amd/microcode.h> +#include <cpu/amd/mtrr.h> #include <cpu/cpu.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> @@ -31,7 +32,11 @@ */ static void pre_mp_init(void) { - x86_setup_mtrrs_with_detect_no_above_4gb(); + const msr_t syscfg = rdmsr(SYSCFG_MSR); + if (!(syscfg.lo & SYSCFG_MSR_TOM2WB)) + x86_setup_mtrrs_with_detect_no_above_4gb(); + else + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); }
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index e0daa33..02956aa 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -1,24 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h> #include <amdblocks/cpu.h> #include <amdblocks/mca.h> #include <amdblocks/reset.h> #include <amdblocks/smm.h> #include <assert.h> -#include <cpu/cpu.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/smm.h> -#include <acpi/acpi.h> -#include <device/device.h> -#include <device/pci_ops.h> -#include <soc/pci_devs.h> -#include <soc/cpu.h> -#include <soc/smi.h> -#include <soc/iomap.h> #include <console/console.h> #include <cpu/amd/microcode.h> +#include <cpu/amd/mtrr.h> +#include <cpu/cpu.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> +#include <device/device.h> +#include <device/pci_ops.h> +#include <soc/cpu.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/smi.h> #include <types.h>
_Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of " @@ -35,7 +36,11 @@ */ static void pre_mp_init(void) { - x86_setup_mtrrs_with_detect_no_above_4gb(); + const msr_t syscfg = rdmsr(SYSCFG_MSR); + if (!(syscfg.lo & SYSCFG_MSR_TOM2WB)) + x86_setup_mtrrs_with_detect_no_above_4gb(); + else + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); }
diff --git a/src/soc/amd/sabrina/cpu.c b/src/soc/amd/sabrina/cpu.c index 5d3539f..e801cea 100644 --- a/src/soc/amd/sabrina/cpu.c +++ b/src/soc/amd/sabrina/cpu.c @@ -10,6 +10,7 @@ #include <assert.h> #include <console/console.h> #include <cpu/amd/microcode.h> +#include <cpu/amd/mtrr.h> #include <cpu/cpu.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> @@ -34,7 +35,11 @@ */ static void pre_mp_init(void) { - x86_setup_mtrrs_with_detect_no_above_4gb(); + const msr_t tom2 = rdmsr(MSR_TOM2); + if (!(tom2.lo & SYSCFG_MSR_TOM2WB)) + x86_setup_mtrrs_with_detect_no_above_4gb(); + else + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); }
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 3cd3a95..b14b375 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -3,20 +3,21 @@ #include <amdblocks/mca.h> #include <amdblocks/reset.h> #include <amdblocks/smm.h> +#include <console/console.h> #include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> #include <cpu/cpu.h> #include <cpu/x86/mp.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci_ops.h> -#include <soc/pci_devs.h> #include <soc/cpu.h> -#include <soc/northbridge.h> -#include <soc/smi.h> #include <soc/iomap.h> -#include <console/console.h> +#include <soc/northbridge.h> +#include <soc/pci_devs.h> +#include <soc/smi.h> #include <types.h>
/* @@ -32,7 +33,11 @@ */ static void pre_mp_init(void) { - x86_setup_mtrrs_with_detect(); + const msr_t syscfg = rdmsr(SYSCFG_MSR); + if (!(syscfg.lo & SYSCFG_MSR_TOM2WB)) + x86_setup_mtrrs_with_detect_no_above_4gb(); + else + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); }