Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33193
Change subject: soc/intel/{cml, whl}: Add option to skip HECI function disable in SMM ......................................................................
soc/intel/{cml, whl}: Add option to skip HECI function disable in SMM
This patch provides an additional option to skip HECI function disabling using SMM mode for WHL and CML platform, where FSP has dedicated UPD to make HECI function disable.
User to select SKIP_HECI_FUNCTION_DISABLE_USING_SMM if FSP has provided dedicated UPD.
Change-Id: If3b064f3c32877235916f966a01beb525156d188 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/smm/Kconfig M src/soc/intel/icelake/smihandler.c 4 files changed, 15 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/33193/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 76906b2..fd87a5f 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -27,6 +27,7 @@ bool default n select SOC_INTEL_COMMON_CANNONLAKE_BASE + select SKIP_HECI_FUNCTION_DISABLE_USING_SMM if CHROMEOS help Intel Whiskeylake support
@@ -34,6 +35,7 @@ bool default n select SOC_INTEL_COMMON_CANNONLAKE_BASE + select SKIP_HECI_FUNCTION_DISABLE_USING_SMM if CHROMEOS help Intel Cometlake support
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 9af2917..2673bc5 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -88,7 +88,8 @@
config = dev->chip_info;
- if (config->HeciEnabled == 0) + if (!config->HeciEnabled && + !CONFIG(SKIP_HECI_FUNCTION_DISABLE_USING_SMM)) pch_disable_heci(); }
diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig index a58c631..ae522f4 100644 --- a/src/soc/intel/common/block/smm/Kconfig +++ b/src/soc/intel/common/block/smm/Kconfig @@ -23,3 +23,12 @@ Time in milliseconds that SLP_SMI for S5 waits for before enabling sleep. This is required to avoid any race between SLP_SMI and PWRBTN SMI. + +config SKIP_HECI_FUNCTION_DISABLE_USING_SMM + bool + depends on SOC_INTEL_COMMON_BLOCK_SMM + default n + help + This Kconfig will help to skip HECI function disable using + SMM mode. User to only select this option if FSP provide + dedicated UPD to perform HECI function disable. diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 5c00b63..60e7f80 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -86,7 +86,8 @@
config = dev->chip_info;
- if (config->HeciEnabled == 0) + if (!config->HeciEnabled && + !CONFIG(SKIP_HECI_FUNCTION_DISABLE_USING_SMM)) pch_disable_heci(); }