[coreboot-gerrit] Change in coreboot[master]: soc/amd/common: Correct SPI FIFO size check

[Aaron Durbin (Code Review)]

Aaron Durbin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37721 )

Change subject: soc/amd/common: Correct SPI FIFO size check
......................................................................

soc/amd/common: Correct SPI FIFO size check

When checking that command and data fit in the FIFO, don't count the first
byte.  The command doesn't go through the FIFO.

TEST=confirm error (4+68>71) goes away on Mandolin
BUG=b:146225550

Change-Id: Ica2ca514deea401c9c5396913087e07a12ab3cf3
Signed-off-by: Marshall Dawson 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37721
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
Reviewed-by: Eric Peers 
Reviewed-by: Frans Hendriks 
Reviewed-by: Martin Roth 
---
M src/soc/amd/common/block/spi/fch_spi_flash.c
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Martin Roth: Looks good to me, approved
  Frans Hendriks: Looks good to me, but someone else must approve
  Raul Rangel: Looks good to me, approved
  Eric Peers: Looks good to me, but someone else must approve

Objections:
  Kyösti Mälkki: I would prefer that you didn't submit this

diff --git a/src/soc/amd/common/block/spi/fch_spi_flash.c b/src/soc/amd/common/block/spi/fch_spi_flash.c
index d8eeefc..b05c1a4 100644
--- a/src/soc/amd/common/block/spi/fch_spi_flash.c
+++ b/src/soc/amd/common/block/spi/fch_spi_flash.c
@@ -40,7 +40,8 @@
    int ret;
    u8 buff[SPI_FIFO_DEPTH + 1];

-	if ((cmd_len + data_len) > SPI_FIFO_DEPTH)
+	/* Ensure FIFO is large enough.  First byte of command does not go in the FIFO. */
+	if ((cmd_len - 1 + data_len) > SPI_FIFO_DEPTH)
    	return -1;
    memcpy(buff, cmd, cmd_len);
    memcpy(buff + cmd_len, data, data_len);