[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add ACPI entry for LAN

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/28743

Change subject: soc/intel/cannonlake: Add ACPI entry for LAN
......................................................................

soc/intel/cannonlake: Add ACPI entry for LAN

Add ACPI DSDT entry for integrated Gigabit LAN controller.

Change-Id: I15bf1d4065894531871380b3318f553b637f4a97
Signed-off-by: Lijian Zhao 
---
A src/soc/intel/cannonlake/acpi/pch_glan.asl
M src/soc/intel/cannonlake/acpi/southbridge.asl
2 files changed, 33 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/28743/1

diff --git a/src/soc/intel/cannonlake/acpi/pch_glan.asl b/src/soc/intel/cannonlake/acpi/pch_glan.asl
new file mode 100644
index 0000000..260dd44
--- /dev/null
+++ b/src/soc/intel/cannonlake/acpi/pch_glan.asl
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017-2108 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Gigabit Ethernet Controller 0:1f.6 */
+
+Device (GLAN)
+{
+	Name (_ADR, 0x001f0006)
+
+	Name (_S0W, 3)
+
+	Name (_PRW, Package() {GPE0_PME_B0, 4})
+
+	Method (_DSW, 3) {}
+}
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index e4f29b6..6fac398 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017 Intel Corp.
+ * Copyright (C) 2017-2018 Intel Corp.
  * (Written by Bora Guvendik  for Intel Corp.)
  *
  * This program is free software; you can redistribute it and/or modify
@@ -48,3 +48,6 @@

/* CNVi */
 #include "cnvi.asl"
+
+/* GBe 0:1f.6 */
+#include "pch_glan.asl"