[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE

[Tim Wawrzynczak (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Nick Vaccaro, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39706

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE
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soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE

According to the latest Tigerlake Platform FSP Integration Guide, the
minimum amount of stack needed for FSP-M is 256KiB. Change
DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined
empirically). JSL requires 192KiB.

Signed-off-by: Tim Wawrzynczak 
Change-Id: Ic9be6446c4db7f62479deab06ebeba2c7326e681
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 4 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/39706/2