[coreboot-gerrit] Patch set updated for coreboot: 059746c AMD S3 resume: Add framwork to write bigger data

[Siyuan Wang]

Siyuan Wang ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3413

-gerrit

commit 059746c58cdf66a520426b82dfbb9583d79fdd55
Author: Siyuan Wang 
Date:   Sat Jun 8 10:25:06 2013 +0800

AMD S3 resume: Add framwork to write bigger data

This patch is based on 'AMD S3: Program the flash in a bigger data packet'[1]

Some AMD south bridge can write bigger data when saving S3 info.
    In this patch, I use macro 'SB_SPI_TX_LEN' to contral data size.

I have tested on AMD Parmer and Thatcher. We will relase a new board
    whose south bridge can transfer more than 4 bytes each time.

[1] http://review.coreboot.org/#/c/2306/

Change-Id: Id984955d46eae487e39d45979f1a90054aa9f54b
    Signed-off-by: Siyuan Wang 
    Signed-off-by: Siyuan Wang 
---
 src/cpu/amd/agesa/s3_resume.c          | 22 ++++++++++++++++++++--
 src/southbridge/amd/agesa/hudson/spi.c |  8 ++++++++
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 8a9ffee..c957cdc 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -152,10 +152,22 @@ void write_mtrr(struct spi_flash *flash, u32 *p_nvram_pos, unsigned idx)
 {
    msr_t  msr_data;
    msr_data = rdmsr(idx);
+
+#ifdef SB_SPI_TX_LEN
+#define SPI_SIZE_MTRR SB_SPI_TX_LEN
+#else
+#define SPI_SIZE_MTRR 4
+#endif
+
+#if SPI_SIZE_MTRR >= 8
+	flash->write(flash, *p_nvram_pos, 8, &msr_data);
+	*p_nvram_pos += 8;
+#else
    flash->write(flash, *p_nvram_pos, 4, &msr_data.lo);
    *p_nvram_pos += 4;
    flash->write(flash, *p_nvram_pos, 4, &msr_data.hi);
    *p_nvram_pos += 4;
+#endif
 }
 #endif

@@ -264,10 +276,16 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
    nvram_pos = 0;
    flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize);

-	for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) {
+#ifdef SB_SPI_TX_LEN
+#define SPI_DATA_PACKET_SIZE SB_SPI_TX_LEN
+#else
+#define SPI_DATA_PACKET_SIZE 4
+#endif
+	for (nvram_pos = 0; nvram_pos < DataSize - SPI_DATA_PACKET_SIZE; nvram_pos += SPI_DATA_PACKET_SIZE) {
    	data = *(u32 *) (Data + nvram_pos);
-		flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos));
+		flash->write(flash, nvram_pos + pos + 4, SPI_DATA_PACKET_SIZE, (u8 *)(Data + nvram_pos));
    }
+	flash->write(flash, nvram_pos + pos + 4, DataSize % SPI_DATA_PACKET_SIZE, (u8 *)(Data + nvram_pos));

flash->spi->rw = SPI_WRITE_FLAG;
    spi_release_bus(flash->spi);
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index 1a63ce2..bcc280a 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -31,6 +31,14 @@
 static int bus_claimed = 0;
 #endif

+/*
+ * SB_SPI_TX_LEN is the biggest data size which south bridge can transfer.
+ * This size does not include SPI command.
+ */
+#ifndef SB_SPI_TX_LEN
+#define SB_SPI_TX_LEN 4
+#endif
+
 static u32 spibar;

static void reset_internal_fifo_pointer(void)