Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
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Patch Set 65:
(1 comment)
Patchset:
PS65:
@Subrata, could you elaborate the expect PCIE CLK setting for FSP? Can we disable all by default? Or […]
I need little time Eric, things are not exact match when i'm reading spec and FSP code. As per FSP, SoC has access to 10 CLKSRC hence FSP can disable those CLKSRC and thats what i'm seeing when CLKSRC[8] is getting disable, i'm seeing x4 port is not working. Need to understand it better
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