Maxim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83019?usp=email )
Change subject: util/superiotool/fintek: Add f81966 register table ......................................................................
util/superiotool/fintek: Add f81966 register table
In accordance with the F81962/F81964/F81966/F81967 datasheet: Release Date: Feb, 2018, Version: V0.18P
This chip is under NDA, but some motherboard manufacturers provide documentation in the public [1].
Register-selectors are the same as in the f81866 chip[2].
[1] http://www.jetwaycomputer.com/download/Fintek/F81966_wdt_gpio.zip [2] CB:83004
Change-Id: Ic3418c337883538e47eb181cbe1ad2dc828e12a1 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M util/superiotool/fintek.c 1 file changed, 79 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83019/1
diff --git a/util/superiotool/fintek.c b/util/superiotool/fintek.c index ac05ae4..330d407 100644 --- a/util/superiotool/fintek.c +++ b/util/superiotool/fintek.c @@ -10,6 +10,7 @@
#define FINTEK_VENDOR_ID 0x3419 #define FINTEK_F81866_DID 0x1010 +#define FINTEK_F81966_DID 0x0215
#define CFG_SEL(bank_prog_sel, clk_tune_prog) \ ((sel_##bank_prog_sel##_en & 0x3) << 3 | (clk_tune_prog_##clk_tune_prog & 0x1)) @@ -516,12 +517,81 @@ {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf4,0xf5,0xf6,EOT}, {NANA,0x00,0x00,NANA,NANA,0x04,NANA,0x00,0x00,0x00,EOT}}, {EOT}}}, - {0x0215, "F81804/F81962/F81964/F81966/F81967", { + {FINTEK_F81966_DID, "F81804/F81962/F81964/F81966/F81967", { + {NOLDN, NULL, /* Global Control Registers (selectable) */ + {EXT_SELECTOR, 0x02,0x07,0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,EXT_SELECTOR, 0x28,0x2a,0x2b,0x2c,EXT_SELECTOR, 0x28,0x2a,0x2b,0x2c,EXT_SELECTOR, 0x28,0x2a,0x2b,0x2c,EXT_SELECTOR, 0x29,0x2c,0x2b,0x2c,EXT_SELECTOR, EOT}, + {CFG_SEL(bank0, dis),NANA,0x00,0x15,0x02,0x19,0x34,0x00,0x23,0x02,0xa0,0x00,0x00,0x02,0x0c,0x28,CFG_SEL(bank1, dis),0x00,0x00,0x00,0x00,CFG_SEL(bank2, dis),0x03,0x60,0x00,0x00,CFG_SEL(bank3, dis),0x5b,0x03,0x00,0x18,CFG_SEL(bank0, en),0x03,0xe7,NANA,0x00,CFG_SEL(bank0, dis), EOT}}, + {0x03, "LPT", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {NANA,0x03,0x78,0x07,0x03,0xc2,EOT}}, + {0x04, "HWMON", + {0x30,0x60,0x61,0x70,EOT}, + {NANA,0x02,0x95,NANA,EOT}}, + {0x05, "KBC", + {0x30,0x60,0x61,0x70,0x72,0xfe,EOT}, + {NANA,0x00,0x60,NANA,NANA,0x00,EOT}}, + {0x06, "GPIO", + {0x30,0x60,0x61,0x70,0x71,0x72,0x73,0x7e,0x7f, 0xf0,0xf1,0xf2,0xf3,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8, 0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6, 0xd0,0xd1,0xd2, 0xc0,0xc1,0xc2,0xc3, 0xb0,0xb1,0xb2,0xb3, 0xa0,0xa1,0xa2,0xa4,0xa5,0xa6, 0x90,0x91,0x92,0x93, 0x80,0x81,0x82,0x83, 0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e, 0x98,0x99,0x9a,0x9b, EOT}, + {NANA,0x00,0x60,NANA,NANA,NANA,NANA,0x00,0x00, 0x00,0x0f,NANA,0x00,0x00,0x00,0xff,0x00,0x00,0x00, 0x00,0xff,NANA,0x00,0x00,0xff,0x00, 0x00,0xff,NANA, 0x00,0xff,NANA,0x00, 0x00,0xff,NANA,0x00, 0x00,0xff,NANA,0x00,0xff,0x00, 0x00,0xff,NANA,0x00, 0x00,0xff,NANA,0x00, 0x00,0xff,NANA,0x00,0x00,0xff,0x00, 0x00,0xff,NANA,0x00, EOT}}, + {0x07, "WDT", + {0x30,0x60,0x61,0xf0,0xf5,0xf6,0xfa,EOT}, + {NANA,0x00,0x00,0x00,0x00,0x00,NANA,EOT}}, + {0x0a, "PME, ACPI & ERP", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xec,0xed,0xee,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf8,0xf9,0xfa,0xfc,0xfd,0xfe,EOT}, + {NANA,0x00,0x0c,0x8c,0xc3,0x09,0xc7,0x09,0x63,0x00,0x0f,0x14,0x00,0x00,0x00,NANA,0x00,NANA,0x07,0x1c,0x00,0x00,0x00,0x00,0x07,0x00,0x00,EOT}}, + {0x0f, "SPI Master", + {0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x03,EOT}}, + {0x10, "UART1", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,0xf6,0xf7,0xf8,0xfe,0xff,EOT}, + {NANA,0x03,0xf8,NANA,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0xff,EOT}}, + {0x11, "UART2", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,0xf6,0xf7,0xf8,0xfe,0xff,EOT}, + {NANA,0x02,0xf8,NANA,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0xff,EOT}}, + {0x12, "UART3", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,0xf6,0xf7,0xf8,0xfe,0xff,EOT}, + {NANA,0x03,0xe8,NANA,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0xff,EOT}}, + {0x13, "UART4", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,0xf6,0xf7,0xf8,0xfe,0xff,EOT}, + {NANA,0x02,0xe8,NANA,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0xff,EOT}}, + {0x14, "UART5", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,0xf6,0xf7,0xf8,0xfe,0xff,EOT}, + {NANA,0x00,0x00,NANA,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0xff,EOT}}, + {0x15, "UART6", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,0xf6,0xf7,0xf8,0xfe,0xff,EOT}, + {NANA,0x00,0x00,NANA,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0xff,EOT}}, {EOT}}}, {EOT} };
static const struct superio_registers hwm_table[] = { + {FINTEK_F81966_DID, "F81804/F81962/F81964/F81966/F81967", { + {NOLDN, NULL, /* 5.4.6 Hardware Monitor General Setting & 5.4.13 PECI/TSI/I2C Setting */ + {0x01,0x02,0x03,0x04,0x05,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,EOT}, + {0x03,0x00,0x00,0x00,0x00,0x00,0x4c,0x00,0x00,0x00,0x55,0x00,0x00,0x02,EOT}}, + {NOLDN, NULL, /* 5.4.22 PECI Command Setting */ + {0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,EOT}, + {0x44,0x00,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {NOLDN, NULL, /* 5.4.39 TSI/MXM Temperature */ + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,EOT}, + {NANA,NANA,NANA,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,0x01,0x00,EOT}}, + {NOLDN, NULL, /* 5.4.56 Temperature Related Register */ + {0x60,0x61,0x62,0x63,0x64,0x66,0x6b,0x6c,0x6d,0x6f,0x7f,0x72,0x74,0x7a,0x7b,0x7e,0x80,0x81,0x82,0x83,0x84,0x85,EOT}, + {NANA,NANA,NANA,0x03,0x00,0x02,0x06,0x04,NANA,0x00,0x00,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, /* 5.4.69 Voltage Setting */ + {0x10,0x11,0x12,0x14,0x15,0x16,0x17,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x2d,0x2e,0x2f,0x30,0x31,0x36,0x37,0x38,0x39,0x3a,0x3f,EOT}, + {0x00,0x00,0x06,0x00,0x00,0x00,0x00,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,0x00,EOT}}, + {NOLDN, NULL, /* 5.4.79 General Fan Control Setting (selectable) */ + {EXT_SELECTOR, 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9a,0x9b,0x9c,0x9d,0x9e,0x9f,EXT_SELECTOR, 0x94,0x96,0x97,0x9a,0x9b,EXT_SELECTOR, EOT}, + {HWM_FAN_SEL(dis),0x00,RSVD,RSVD,0x00,0x00,NANA,0x15,0x00,0x44,0x02,0x00,0x19,0x55,0x05,NANA,0x0a,HWM_FAN_SEL(en),0x05,0x00,0x00,0x00,0x19,HWM_FAN_SEL(dis),EOT}}, + {NOLDN, NULL, /* 5.4.101 FAN1 Control Register */ + {0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7,0xa8,0xa9,0xaa,0xab,0xac,0xad,0xae,0xaf, /* FAN1 */ + 0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7,0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xbe,0xbf, /* FAN2 */ + 0xc0,0xc1,0xc2,0xc3,0xc4,0xc5,0xc6,0xc7,0xc8,0xc9,0xca,0xcb,0xcc,0xcd,0xce,0xcf, /* FAN3 */ EOT}, + {0x0f,0xff,0x00,0x80,0x03,0xff,0x3c,0x32,0x28,0x1e,0xff,0xd9,0xb2,0x99,0x80,0x1d, /* FAN1 */ + 0x0f,0xff,0x00,0x80,0x03,0xff,0x3c,0x32,0x28,0x1e,0xff,0xd9,0xb2,0x99,0x80,0x1d, /* FAN2 */ + 0x0f,0xff,0x00,0x80,0x03,0xff,0x3c,0x32,0x28,0x1e,0xff,0xd9,0xb2,0x99,0x80,0x1d, /* FAN3 */ EOT}}, + {EOT}}}, {FINTEK_F81866_DID, "F81866", { {NOLDN, NULL, /* 6.4.2.1 Configuration Setting & 6.4.2.2 */ {0x01,0x02,0x03,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0f,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xec,0xed,0xee,0xef,EOT}, @@ -603,7 +673,7 @@ {EOT} };
-void f81866_extra_selector_cb(uint16_t port, uint8_t ldn, int16_t sel_val, bool silent) +void f81866_f81966_ext_sel_cb(uint16_t port, uint8_t ldn, int16_t sel_val, bool silent) { const uint8_t port_select_reg_addr = 0x27; uint8_t val; @@ -623,7 +693,7 @@ port_select_reg_addr, (val & 0xc) >> 2, val & 0x1); }
-void f81866_hwm_extra_selector_cb(uint16_t hwmport, uint8_t ldn, int16_t sel_val, bool silent) +void f81866_f81966_hwm_ext_sel_cb(uint16_t hwmport, uint8_t ldn, int16_t sel_val, bool silent) { const uint8_t fan_select_reg_addr = 0x9f; uint8_t val; @@ -663,8 +733,8 @@ get_superio_name(reg_table, did), vid, did, port); chip_found = 1;
- if (did == FINTEK_F81866_DID) - sel_cb = f81866_extra_selector_cb; + if (did == FINTEK_F81866_DID || did == FINTEK_F81966_DID) + sel_cb = f81866_f81966_ext_sel_cb;
dump_superio("Fintek", reg_table, port, did, LDN_SEL, sel_cb);
@@ -679,8 +749,8 @@ /* HWM address register = HWM base address + 5. */ hwmport += 5;
- if (did == FINTEK_F81866_DID) - sel_cb = f81866_hwm_extra_selector_cb; + if (did == FINTEK_F81866_DID || did == FINTEK_F81966_DID) + sel_cb = f81866_f81966_hwm_ext_sel_cb;
printf("Hardware monitor (0x%04x)\n", hwmport); dump_superio("Fintek-HWM", hwm_table, hwmport, did, LDN_SEL, sel_cb); @@ -716,8 +786,8 @@ get_superio_name(reg_table, did), vid, did, port); chip_found = 1;
- if (did == FINTEK_F81866_DID) - sel_cb = f81866_extra_selector_cb; + if (did == FINTEK_F81866_DID || did == FINTEK_F81966_DID) + sel_cb = f81866_f81966_ext_sel_cb;
dump_superio("Fintek", reg_table, port, did, LDN_SEL, sel_cb);