[coreboot-gerrit] Change in coreboot[master]: [WIP]soc/intel/cfl: Try to enable Intel DCI

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39692 )

Change subject: [WIP]soc/intel/cfl: Try to enable Intel DCI
......................................................................

[WIP]soc/intel/cfl: Try to enable Intel DCI

Enable DCI using P2SB interface as documented in Document Number:
332691-003EN "Intel 100 Series and Intel C230 Series Chipset Family
Platform Controller Hub (PCH) Vol2"

Enable CPU debugging using MSR IA32_DEBUG_INTERFACE.

Intel DCI needs hardware support and doesn't work on every mainboard.

Tested: Doesn't work.

Change-Id: I2c8bf7e82116bc44430f4be4498f2e445f904886
Signed-off-by: Patrick Rudolph 
---
M src/arch/x86/include/arch/cpu.h
M src/include/cpu/x86/msr.h
M src/soc/intel/cannonlake/bootblock/cpu.c
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/include/soc/pcr_ids.h
6 files changed, 36 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/39692/1

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index e149c38..d27fcc4 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -151,6 +151,7 @@
 #define X86_VENDOR_UNKNOWN 0xff

#define CPUID_FEATURE_PAE (1 << 6)
+#define CPUID_FEAURE_SDBG (1 << 11)
 #define CPUID_FEATURE_PSE36 (1 << 17)
 #define CPUID_FEAURE_HTT (1 << 28)

diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index c761bc0..24e689f 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -84,6 +84,7 @@
 #define IA32_HWP_CAPABILITIES		0x771
 #define IA32_HWP_REQUEST		0x774
 #define IA32_HWP_STATUS			0x777
+#define IA32_DEBUG_INTERFACE		0xc80
 #define IA32_PQR_ASSOC			0xc8f
 /* MSR bits 33:32 encode slot number 0-3 */
 #define   IA32_PQR_ASSOC_MASK	(1 << 0 | 1 << 1)
diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c
index 0523aa0..1f0fdfd 100644
--- a/src/soc/intel/cannonlake/bootblock/cpu.c
+++ b/src/soc/intel/cannonlake/bootblock/cpu.c
@@ -15,6 +15,8 @@
 #include <intelblocks/cpulib.h>
 #include <intelblocks/fast_spi.h>
 #include <soc/bootblock.h>
+#include <cpu/x86/msr.h>
+#include <arch/cpu.h>

void bootblock_cpu_init(void)
 {
@@ -22,4 +24,13 @@
    if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) &&
    	CONFIG(BOOT_DEVICE_SPI_FLASH))
    	fast_spi_cache_bios_region();
+	/*
+	 * Enable processor debugging features. See Intel 64 and IA-32 Architectures SDM
+	 * Document  326019-060US, Table 35-2
+	 */
+	if (CONFIG(SOC_INTEL_DEBUG_CONSENT) &&
+	    (cpu_get_feature_flags_ecx() & CPUID_FEAURE_SDBG)) {
+		msr_t msr = {.lo = 1, .hi = 0};
+		wrmsr(IA32_DEBUG_INTERFACE, msr);
+	}
 }
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 7cff74b..6a94996 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -55,6 +55,9 @@
 #define PCR_DMI_LPCIOD		0x2770
 #define PCR_DMI_LPCIOE		0x2774

+#define PCR_DCI_ECTRL		0x4
+#define PCR_DCI_HDCIEN		(1 << 4)
+
 static uint32_t get_pmc_reg_base(void)
 {
    uint8_t pch_series;
@@ -94,6 +97,21 @@
    write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN);
 }

+static void pch_enable_dci(bool enable)
+{
+	/*
+	 * Enable Intel DCI. See Intel
+	 * Intel 100 Series and Intel C230 Series Chipset Family Platform Controller Hub
+	 * (PCH), Chapter 31.3.1
+	 */
+	uint32_t dci_control = pcr_read32(PID_DCI, PCR_DCI_ECTRL);
+	if (enable)
+		dci_control |= PCR_DCI_HDCIEN;
+	else
+		dci_control &= ~PCR_DCI_HDCIEN;
+	pcr_write32(PID_DCI, PCR_DCI_ECTRL, dci_control);
+}
+
 void bootblock_pch_early_init(void)
 {
    fast_spi_early_init(SPI_BASE_ADDRESS);
@@ -196,4 +214,6 @@

/* GPIO community PM configuration */
    soc_gpio_pm_configuration();
+
+	pch_enable_dci(CONFIG(SOC_INTEL_DEBUG_CONSENT));
 }
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 4634806..ca2094a 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -296,6 +296,8 @@
    if (dev) {
    	if (!xdci_can_enable())
    		dev->enabled = 0;
+		if (CONFIG(SOC_INTEL_DEBUG_CONSENT))
+			dev->enabled = 1;
    	params->XdciEnable = dev->enabled;
    } else
    	params->XdciEnable = 0;
diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
index 99c37bc..d87d562 100644
--- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
@@ -28,6 +28,7 @@
 #define PID_PSTH	0x89
 #define PID_CSME0	0x90
 #define PID_ISCLK	0xad
+#define PID_DCI		0xb8
 #define PID_PSF1	0xba
 #define PID_PSF2	0xbb
 #define PID_PSF3	0xbc