[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/sata: Fix SATA detection issue between Ports 3-7

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41674 )

Change subject: soc/intel/common/block/sata: Fix SATA detection issue between Ports 3-7
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Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/41674/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/41674/1//COMMIT_MSG@10 
PS1, Line 10: on Intel H-PCH.
> Is there a bug report for that? Please elaborate why the range is increased.

Ack

https://review.coreboot.org/c/coreboot/+/41674/1/src/soc/intel/common/block/... 
File src/soc/intel/common/block/sata/sata.c:

https://review.coreboot.org/c/coreboot/+/41674/1/src/soc/intel/common/block/... 
PS1, Line 44: port_impl &= 0xFF; /* bit 0-7 */
> I think we can remove this line now. port_impl(u8) would be 8 bit read from config space.

Ack