Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29053
Change subject: soc/amd: Implement common reset API ......................................................................
soc/amd: Implement common reset API
Add an `amdblocks` internal API and rename soft_reset() => warm_reset() hard_reset() => cold_reset() as these terms are commonly used in the surrounding code.
On Stoney Ridge, make board_reset() call cold_reset() to keep current behaviour of common code calling hard_reset(). But add a TODO if this is intended.
Note: Stoney Ridge is using CF9 for the actual reset but the configuration for a cold reset doesn't use the usual full reset bit but some other mechanism.
Change-Id: Id33eda676d79529db759b85fa8e28386846e6fa4 Signed-off-by: Nico Huber nico.h@gmx.de --- A src/soc/amd/common/block/include/amdblocks/reset.h M src/soc/amd/common/block/pi/def_callouts.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/reset.c M src/soc/amd/stoneyridge/southbridge.c 5 files changed, 56 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/29053/1
diff --git a/src/soc/amd/common/block/include/amdblocks/reset.h b/src/soc/amd/common/block/include/amdblocks/reset.h new file mode 100644 index 0000000..4f149ea --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/reset.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMD_RESET_H__ +#define __AMD_RESET_H__ + +#include <console/console.h> +#include <arch/cache.h> +#include <halt.h> + +void do_warm_reset(void); +void do_cold_reset(void); + +static inline __noreturn void warm_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + dcache_clean_all(); + do_warm_reset(); + halt(); +} + +static inline __noreturn void cold_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + dcache_clean_all(); + do_cold_reset(); + halt(); +} + +#endif /* __AMD_RESET_H__ */ diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index d136084..27d4b0b 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -21,7 +21,7 @@ #include <amdblocks/BiosCallOuts.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> -#include <reset.h> +#include <amdblocks/reset.h> #include <soc/southbridge.h>
#if ENV_BOOTBLOCK @@ -127,12 +127,12 @@ switch (ResetType) { case WARM_RESET_WHENEVER: case WARM_RESET_IMMEDIATELY: - do_soft_reset(); + warm_reset(); break;
case COLD_RESET_WHENEVER: case COLD_RESET_IMMEDIATELY: - do_hard_reset(); + cold_reset(); break;
default: diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 1f2331a..4411984 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -39,7 +39,6 @@ select GENERIC_UDELAY select IOAPIC select HAVE_USBDEBUG_OPTIONS - select HAVE_HARD_RESET select HAVE_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select TSC_SYNC_LFENCE diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c index 738ec59..34aa576 100644 --- a/src/soc/amd/stoneyridge/reset.c +++ b/src/soc/amd/stoneyridge/reset.c @@ -20,6 +20,7 @@ #include <soc/pci_devs.h> #include <device/pci_ops.h> #include <soc/southbridge.h> +#include <amdblocks/reset.h>
void set_warm_reset_flag(void) { @@ -45,7 +46,7 @@ pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic); }
-void do_hard_reset(void) +void do_cold_reset(void) { clear_bios_reset();
@@ -55,7 +56,7 @@ outb(RST_CMD | SYS_RST, SYS_RESET); }
-void do_soft_reset(void) +void do_warm_reset(void) { set_warm_reset_flag(); clear_bios_reset(); @@ -63,3 +64,9 @@ /* Assert reset signals only. */ outb(RST_CMD | SYS_RST, SYS_RESET); } + +void do_board_reset(void) +{ + /* TODO: Would a warm_reset() suffice? */ + do_cold_reset(); +} diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 763ddd7..5dff9fc 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -26,6 +26,7 @@ #include <elog.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/agesawrapper.h> +#include <amdblocks/reset.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <soc/amd_pci_int_defs.h> @@ -33,7 +34,6 @@ #include <soc/pci_devs.h> #include <agesa_headers.h> #include <soc/nvs.h> -#include <reset.h>
/* * Table of devices that need their AOAC registers enabled and waited @@ -638,7 +638,7 @@ setup_misc(&reboot);
if (reboot) - soft_reset(); + warm_reset();
sb_enable_legacy_io(); enable_aoac_devices();