Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/11791 )
Change subject: mainboard/lenovo/t410: Add new port ......................................................................
mainboard/lenovo/t410: Add new port
The port is based on the x201 / t410s. 2537-vg5 / i5, no discrete gpu
Tested and working: * Native raminit * Native gfxinit * Booting Seabios 1.12.1 * Booting from EHCI * Running GNU/Linux 5.0.0 * No errors in dmesg * EHCI debug on the devices left side, bottom-right * Keyboard * Fn keys (Mute, Volume, Mic) * Touchpad * TPM * Wifi * Sound * USB * Ethernet * S3 resume * VBOOT
Testing in progress.
Untested: * VGA * Displayport * Docking station
Bugs: * AC adapter can't be read from ACPI * TPM not working with VBOOT and C_ENV BB
Details for flashing externally: 1. Disconnect all power 2. Connect the external flasher 3. Connect the power cord (This fixes internal power control) 4. Remove the power cord
Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Signed-off-by: Nicolas Reinecke nr@das-labor.org Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/11791 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/t410.md A Documentation/mainboard/lenovo/t410_chip_location.jpg A src/mainboard/lenovo/t410/Kconfig A src/mainboard/lenovo/t410/Kconfig.name A src/mainboard/lenovo/t410/Makefile.inc A src/mainboard/lenovo/t410/acpi/dock.asl A src/mainboard/lenovo/t410/acpi/ec.asl A src/mainboard/lenovo/t410/acpi/gpe.asl A src/mainboard/lenovo/t410/acpi/platform.asl A src/mainboard/lenovo/t410/acpi/superio.asl A src/mainboard/lenovo/t410/acpi_tables.c A src/mainboard/lenovo/t410/board_info.txt A src/mainboard/lenovo/t410/cmos.default A src/mainboard/lenovo/t410/cmos.layout A src/mainboard/lenovo/t410/data.vbt A src/mainboard/lenovo/t410/devicetree.cb A src/mainboard/lenovo/t410/dock.c A src/mainboard/lenovo/t410/dock.h A src/mainboard/lenovo/t410/dsdt.asl A src/mainboard/lenovo/t410/early_init.c A src/mainboard/lenovo/t410/gma-mainboard.ads A src/mainboard/lenovo/t410/gpio.c A src/mainboard/lenovo/t410/hda_verb.c A src/mainboard/lenovo/t410/mainboard.c A src/mainboard/lenovo/t410/romstage.c A src/mainboard/lenovo/t410/smihandler.c A src/mainboard/lenovo/t410/thermal.h A src/mainboard/lenovo/t410/vboot-rwa.fmd 29 files changed, 1,483 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 83189757..c9204f6 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -68,6 +68,10 @@ - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md)
+### Nehalem series + +- [T410](lenovo/t410.md) + ### Sandy Bridge series
- [T420](lenovo/t420.md) @@ -82,6 +86,10 @@ - [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md) - [T431s](lenovo/t431s.md)
+## Portwell + +- [PQ7-M107](portwell/pq7-m107.md) + ## MSI
- [MS-7707](msi/ms7707/ms7707.md) diff --git a/Documentation/mainboard/lenovo/t410.md b/Documentation/mainboard/lenovo/t410.md new file mode 100644 index 0000000..980c959 --- /dev/null +++ b/Documentation/mainboard/lenovo/t410.md @@ -0,0 +1,44 @@ +# Lenovo T410 + +## Known issues +* Dock has wrong ACPI ID (causes "AC adapter state cannot be read" in Linux) +* TPM not working with VBOOT and C_ENV bootblock (works without C_ENV BB) + +## Flashing instructions +```eval_rst ++---------------------+--------------------------------+ +| Type | Value | ++=====================+================================+ +| Socketed flash | no | ++---------------------+--------------------------------+ +| Size | 8 MiB | ++---------------------+--------------------------------+ +| In circuit flashing | Only in S3/WoL | ++---------------------+--------------------------------+ +| Package | SOIC-8 | ++---------------------+--------------------------------+ +| Write protection | No | ++---------------------+--------------------------------+ +| Dual BIOS feature | No | ++---------------------+--------------------------------+ +| Internal flashing | Yes | ++---------------------+--------------------------------+ +``` + +The flash IC is located at the bottom center of the mainboard. Sadly, +access to the IC is blocked by the magnesum frame, so you need to disassemble +the entire laptop and remove the mainboard. + +Below is a picture of IC on the mainboard, with the pinouts labeled. + + + +The chip will either be a Macronix MX25L6405D or a Winbond W25Q64CVSIG. +Do not rely on dots painted in the corner of the chip (such as the blue dot +pictured) to orient the pins! + +[Flashing tutorial](../../flash_tutorial/no_ext_power.md) + +Steps to access the flash IC are described here [T4xx series]. + +[T4xx series]: t4xx_series.md diff --git a/Documentation/mainboard/lenovo/t410_chip_location.jpg b/Documentation/mainboard/lenovo/t410_chip_location.jpg new file mode 100644 index 0000000..96bbbcb --- /dev/null +++ b/Documentation/mainboard/lenovo/t410_chip_location.jpg Binary files differ diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig new file mode 100644 index 0000000..329d08d --- /dev/null +++ b/src/mainboard/lenovo/t410/Kconfig @@ -0,0 +1,69 @@ +if BOARD_LENOVO_T410 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select NORTHBRIDGE_INTEL_NEHALEM + select SOUTHBRIDGE_INTEL_IBEXPEAK + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select INTEL_INT15 + select HAVE_ACPI_RESUME + select DRIVERS_LENOVO_WACOM + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select DRIVERS_LENOVO_HYBRID_GRAPHICS + select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION + select H8_HAS_BAT_TRESHOLDS_IMPL + select MAINBOARD_HAS_LIBGFXINIT + +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + +config MAINBOARD_DIR + string + default lenovo/t410 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad T410" + +config USBDEBUG_HCD_INDEX + int + default 2 + +config MAX_CPUS + int + default 8 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config DRAM_RESET_GATE_GPIO + int + default 10 + +endif diff --git a/src/mainboard/lenovo/t410/Kconfig.name b/src/mainboard/lenovo/t410/Kconfig.name new file mode 100644 index 0000000..d79cf39 --- /dev/null +++ b/src/mainboard/lenovo/t410/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_T410 + bool "ThinkPad T410" diff --git a/src/mainboard/lenovo/t410/Makefile.inc b/src/mainboard/lenovo/t410/Makefile.inc new file mode 100644 index 0000000..5615f30 --- /dev/null +++ b/src/mainboard/lenovo/t410/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += early_init.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +romstage-y += dock.c +ramstage-y += dock.c +romstage-y += gpio.c diff --git a/src/mainboard/lenovo/t410/acpi/dock.asl b/src/mainboard/lenovo/t410/acpi/dock.asl new file mode 100644 index 0000000..2bba821 --- /dev/null +++ b/src/mainboard/lenovo/t410/acpi/dock.asl @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle svens@stackframe.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_SB) +{ + Device(DOCK) + { + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { _SB } ) + + Method(_DCK, 1, NotSerialized) + { + if (Arg0) { + /* connect dock */ + Store (1, \GP28) + Store (1, _SB.PCI0.LPCB.EC.DKR1) + Store (1, _SB.PCI0.LPCB.EC.DKR2) + Store (1, _SB.PCI0.LPCB.EC.DKR3) + } else { + /* disconnect dock */ + Store (0, \GP28) + Store (0, _SB.PCI0.LPCB.EC.DKR1) + Store (0, _SB.PCI0.LPCB.EC.DKR2) + Store (0, _SB.PCI0.LPCB.EC.DKR3) + } + Xor(Arg0, _SB.PCI0.LPCB.EC.DKR1, Local0) + Return (Local0) + } + + Method(_STA, 0, NotSerialized) + { + Return (_SB.PCI0.LPCB.EC.DKR1) + } + } +} + +Scope(_SB.PCI0.LPCB.EC) +{ + Method(_Q18, 0, NotSerialized) + { + Notify(_SB.DOCK, 3) + } + + Method(_Q45, 0, NotSerialized) + { + Notify(_SB.DOCK, 3) + } + + Method(_Q58, 0, NotSerialized) + { + Notify(_SB.DOCK, 0) + } + + Method(_Q37, 0, NotSerialized) + { + Notify(_SB.DOCK, 0) + } +} diff --git a/src/mainboard/lenovo/t410/acpi/ec.asl b/src/mainboard/lenovo/t410/acpi/ec.asl new file mode 100644 index 0000000..c00121b --- /dev/null +++ b/src/mainboard/lenovo/t410/acpi/ec.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle svens@stackframe.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/lenovo/h8/acpi/ec.asl> + +#define H8_BAT_THRESHOLDS_BIT7 +#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl> diff --git a/src/mainboard/lenovo/t410/acpi/gpe.asl b/src/mainboard/lenovo/t410/acpi/gpe.asl new file mode 100644 index 0000000..5c900ca --- /dev/null +++ b/src/mainboard/lenovo/t410/acpi/gpe.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle svens@stackframe.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_GPE) +{ + Method(_L18, 0, NotSerialized) + { + /* Read EC register to clear wake status */ + Store(_SB.PCI0.LPCB.EC.WAKE, Local0) + /* So that we don't get a warning that Local0 is unused. */ + Increment (Local0) + } +} diff --git a/src/mainboard/lenovo/t410/acpi/platform.asl b/src/mainboard/lenovo/t410/acpi/platform.asl new file mode 100644 index 0000000..c2cb94c --- /dev/null +++ b/src/mainboard/lenovo/t410/acpi/platform.asl @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + _SB.PCI0.LPCB.EC.MUTE(1) + _SB.PCI0.LPCB.EC.USBP(0) + _SB.PCI0.LPCB.EC.RADI(0) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* Wake the HKEY to init BT/WWAN */ + _SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + + /* Not implemented. */ + Return(Package(){0,0}) +} + +Method(UCMS, 1, Serialized) +{ + Switch(ToInteger(Arg0)) + { + Case (0x0c) /* Turn on ThinkLight */ + { + _SB.PCI0.LPCB.EC.LGHT(1) + } + Case (0x0d) /* Turn off ThinkLight */ + { + _SB.PCI0.LPCB.EC.LGHT(0) + } + } +} diff --git a/src/mainboard/lenovo/t410/acpi/superio.asl b/src/mainboard/lenovo/t410/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/lenovo/t410/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t410/acpi_tables.c b/src/mainboard/lenovo/t410/acpi_tables.c new file mode 100644 index 0000000..2a8d935 --- /dev/null +++ b/src/mainboard/lenovo/t410/acpi_tables.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Vladimir Serbinenko phcoder@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/ibexpeak/nvs.h> +#include "thermal.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + + /* the lid is open by default. */ + gnvs->lids = 1; +} diff --git a/src/mainboard/lenovo/t410/board_info.txt b/src/mainboard/lenovo/t410/board_info.txt new file mode 100644 index 0000000..2d104405 --- /dev/null +++ b/src/mainboard/lenovo/t410/board_info.txt @@ -0,0 +1,5 @@ +Category: laptop +ROM package: SOIC-8 / WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/lenovo/t410/cmos.default b/src/mainboard/lenovo/t410/cmos.default new file mode 100644 index 0000000..5fbc86f --- /dev/null +++ b/src/mainboard/lenovo/t410/cmos.default @@ -0,0 +1,17 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +trackpoint=Enable +fn_ctrl_swap=Disable +sticky_fn=Disable +power_management_beeps=Enable +low_battery_beep=Enable +sata_mode=AHCI +hybrid_graphics_mode=Integrated Only +usb_always_on=Disable diff --git a/src/mainboard/lenovo/t410/cmos.layout b/src/mainboard/lenovo/t410/cmos.layout new file mode 100644 index 0000000..5c7defa --- /dev/null +++ b/src/mainboard/lenovo/t410/cmos.layout @@ -0,0 +1,130 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2013 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +420 1 e 1 low_battery_beep +421 1 e 9 sata_mode +422 2 e 11 usb_always_on +#423 1 r 1 unused + +# coreboot config options: northbridge +424 3 e 10 gfx_uma_size +#427 5 r 0 unused +432 2 e 12 hybrid_graphics_mode + +# VBOOT +448 128 r 0 vbnv + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M +11 0 Disable +11 1 AC and battery +11 2 AC only +12 0 Integrated Only +12 1 Discrete Only + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/lenovo/t410/data.vbt b/src/mainboard/lenovo/t410/data.vbt new file mode 100644 index 0000000..908234e --- /dev/null +++ b/src/mainboard/lenovo/t410/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb new file mode 100644 index 0000000..808e057 --- /dev/null +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -0,0 +1,198 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle svens@stackframe.org +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/nehalem + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "1" + register "gpu_panel_power_up_delay" = "1" + register "gpu_panel_power_down_delay" = "600" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_cpu_backlight" = "0x58d" + register "gpu_pch_backlight" = "0x061a061a" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.link_frequency_270_mhz" = "1" + + device cpu_cluster 0 on + chip cpu/intel/model_2065x + device lapic 0 on end + end + end + + register "pci_mmio_size" = "2048" + + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2193 + end + device pci 01.0 on end # PEG + device pci 02.0 on # VGA controller + subsystemid 0x17aa 0x215a + end + chip southbridge/intel/ibexpeak + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi1_routing" = "2" + register "gpi13_routing" = "2" + + # 0:HDD Bay 1:ODD Bay 4:eSATA Combo Connector + register "sata_port_map" = "0x13" + + register "gpe0_en" = "0x20022046" + register "alt_gp_smi_en" = "0x0000" + register "gen1_dec" = "0x7c1601" # EC + register "gen2_dec" = "0x0c15e1" # PMH7 + register "gen3_dec" = "0x1c1681" # EC ? + register "gen4_dec" = "0x040069" # ? + + register "c2_latency" = "1" + register "docking_supported" = "1" + + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + + device pci 16.0 off end # MEI + device pci 16.2 on # IDE/SATA + subsystemid 0x17aa 0x2161 + end + + device pci 19.0 on # Ethernet + subsystemid 0x17aa 0x2153 + end + + device pci 1a.0 on # USB2 EHCI + subsystemid 0x17aa 0x2163 + end + + device pci 1b.0 on # Audio Controller + subsystemid 0x17aa 0x215e + end + + device pci 1c.0 on end # PCIe Port #1 (wlan) + device pci 1c.1 off end # PCIe Port #2 (wwan) + device pci 1c.2 off end # PCIe Port #3 (wusb) + device pci 1c.3 on end # PCIe Port #4 (ExpressCard) + device pci 1c.4 on + subsystemid 0x17aa 0x2133 + chip drivers/ricoh/rce822 + register "sdwppol" = "1" + register "disable_mask" = "0x87" + device pci 00.0 on + subsystemid 0x17aa 0x2134 + end + end + end # PCIe Port #5 (Ricoh SD & FW) + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 Intel Gigabit Ethernet PHY (not PCIe) + + device pci 1d.0 on # USB2 EHCI + subsystemid 0x17aa 0x2163 + end + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x17aa 0x2166 + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/lenovo/pmh7 + device pnp ff.1 on end # dummy + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa0" + register "config3" = "0xe0" + + register "beepmask0" = "0xfe" + register "beepmask1" = "0x96" + register "has_power_management_beeps" = "1" + + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf4" + register "event5_enable" = "0x3c" + register "event6_enable" = "0x87" + register "event7_enable" = "0x89" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventa_enable" = "0x83" + register "eventb_enable" = "0x00" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x2d" + end + chip drivers/lenovo/hybrid_graphics + device pnp ff.f on end # dummy + + register "detect_gpio" = "21" + + register "has_panel_hybrid_gpio" = "1" + register "panel_hybrid_gpio" = "52" + register "panel_integrated_lvl" = "1" + + register "has_backlight_gpio" = "1" + register "backlight_gpio" = "50" + register "backlight_integrated_lvl" = "0" + + register "has_dgpu_power_gpio" = "1" + register "dgpu_power_gpio" = "49" + register "dgpu_power_off_lvl" = "0" + + register "has_thinker1" = "1" + end + end + device pci 1f.2 on # IDE/SATA + subsystemid 0x17aa 0x2168 + end + device pci 1f.3 on # SMBUS + subsystemid 0x17aa 0x2167 + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + device pci 1f.6 on # Thermal Subsystem + subsystemid 0x17aa 0x2190 + end + end + end +end diff --git a/src/mainboard/lenovo/t410/dock.c b/src/mainboard/lenovo/t410/dock.c new file mode 100644 index 0000000..6b6b206 --- /dev/null +++ b/src/mainboard/lenovo/t410/dock.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * Copyright (C) 2013 Vladimir Serbinenko phcoder@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci_ops.h> +#include <device/device.h> +#include "dock.h" +#include <southbridge/intel/ibexpeak/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <ec/lenovo/h8/h8.h> +#include <ec/acpi/ec.h> + +void h8_mainboard_init_dock(void) +{ + if (dock_present()) { + printk(BIOS_DEBUG, "dock is connected\n"); + dock_connect(); + } else + printk(BIOS_DEBUG, "dock is not connected\n"); +} + +void dock_connect(void) +{ + /* UNTESTED */ + ec_set_bit(0x02, 0); + ec_set_bit(0x1a, 0); + ec_set_bit(0xfe, 4); +} + +void dock_disconnect(void) +{ + /* UNTESTED */ + ec_clr_bit(0x02, 0); + ec_clr_bit(0x1a, 0); + ec_clr_bit(0xfe, 4); +} + +int dock_present(void) +{ + const int gpio_num_array[] = {3, 4, 5, -1}; + + return get_gpios(gpio_num_array) != 7; +} diff --git a/src/mainboard/lenovo/t410/dock.h b/src/mainboard/lenovo/t410/dock.h new file mode 100644 index 0000000..4cd8c85 --- /dev/null +++ b/src/mainboard/lenovo/t410/dock.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THINKPAD_X201_DOCK_H +#define THINKPAD_X201_DOCK_H + +void dock_connect(void); +void dock_disconnect(void); +int dock_present(void); +#endif diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl new file mode 100644 index 0000000..08e2122 --- /dev/null +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define THINKPAD_EC_GPE 17 +#define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE _SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20130325 /* OEM revision */ +) +{ + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + /* Some generic macros */ + #include "acpi/platform.asl" + + /* global NVS and variables */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + /* General Purpose Events */ + #include "acpi/gpe.asl" + + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <northbridge/intel/nehalem/acpi/nehalem.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + Device (UNCR) + { + Name (_BBN, 0xFF) + Name (_ADR, 0x00) + Name (RID, 0x00) + Name (_HID, EisaId ("PNP0A03")) + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* Granularity */ + 0x00FF, /* Range Minimum */ + 0x00FF, /* Range Maximum */ + 0x0000, /* Translation Offset */ + 0x0001, /* Length */ + ,, ) + }) + Device (SAD) + { + Name (_ADR, 0x01) + Name (RID, 0x00) + OperationRegion (SADC, PCI_Config, 0x00, 0x0100) + Field (SADC, DWordAcc, NoLock, Preserve) + { + Offset (0x40), + PAM0, 8, + PAM1, 8, + PAM2, 8, + PAM3, 8, + PAM4, 8, + PAM5, 8, + PAM6, 8 + } + } + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + + /* Dock support code */ + #include "acpi/dock.asl" +} diff --git a/src/mainboard/lenovo/t410/early_init.c b/src/mainboard/lenovo/t410/early_init.c new file mode 100644 index 0000000..63bbe92 --- /dev/null +++ b/src/mainboard/lenovo/t410/early_init.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <delay.h> + +#include <ec/acpi/ec.h> +void bootblock_mainboard_early_init(void) +{ + /* Enable USB Power. We need to do it early for usbdebug to work. */ + ec_set_bit(0x3b, 4); +} diff --git a/src/mainboard/lenovo/t410/gma-mainboard.ads b/src/mainboard/lenovo/t410/gma-mainboard.ads new file mode 100644 index 0000000..9c2a3cb --- /dev/null +++ b/src/mainboard/lenovo/t410/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, -- DP++ connector on the dock + HDMI2, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t410/gpio.c b/src/mainboard/lenovo/t410/gpio.c new file mode 100644 index 0000000..26b27a7 --- /dev/null +++ b/src/mainboard/lenovo/t410/gpio.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, /* DOCK0 */ + .gpio4 = GPIO_MODE_GPIO, /* DOCK1 */ + .gpio5 = GPIO_MODE_GPIO, /* DOCK2 */ + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, /* -SC_DTCT */ + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, /* -1394_DTCT */ + .gpio17 = GPIO_MODE_GPIO, /* DGFX_PWRGD */ + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio18 = GPIO_NO_BLINK, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_NATIVE, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_GPIO, /* PLANARID0 */ + .gpio37 = GPIO_MODE_GPIO, /* PLANARID1 */ + .gpio38 = GPIO_MODE_GPIO, /* PLANARID2 */ + .gpio39 = GPIO_MODE_GPIO, /* PLANARID3 */ + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_GPIO, /* -MDC_KILL */ + .gpio42 = GPIO_MODE_GPIO, /* SMB_3B_EN */ + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, /* -BDC_PRESENCE */ + .gpio49 = GPIO_MODE_GPIO, /* GFX_PWR_EN_D */ + .gpio50 = GPIO_MODE_GPIO, /* BKLT_CTRL_SEL */ + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_GPIO, /* DISCRETE_ENABLE */ + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, /* DDC_MUX_SEL */ + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, /* -DEBUGCARD */ + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_NATIVE, + .gpio69 = GPIO_MODE_NATIVE, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .reset = &pch_gpio_set1_reset, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; diff --git a/src/mainboard/lenovo/t410/hda_verb.c b/src/mainboard/lenovo/t410/hda_verb.c new file mode 100644 index 0000000..752e5da --- /dev/null +++ b/src/mainboard/lenovo/t410/hda_verb.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License, + * or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ + 0x17AA214C, /* Subsystem ID */ + 0x0000000B, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(0x0, 0x17AA214C), + AZALIA_PIN_CFG(0x0, 0x19, 0x042110F0), + AZALIA_PIN_CFG(0x0, 0x1A, 0x61A190F0), + AZALIA_PIN_CFG(0x0, 0x1B, 0x04A110F0), + AZALIA_PIN_CFG(0x0, 0x1C, 0x612140F0), + AZALIA_PIN_CFG(0x0, 0x1D, 0x40F001F0), + AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0), + AZALIA_PIN_CFG(0x0, 0x1F, 0x901701F0), + AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0), + AZALIA_PIN_CFG(0x0, 0x22, 0x40F001F0), + AZALIA_PIN_CFG(0x0, 0x23, 0x90A601F0), + + 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ + 0x17AA21B5, /* Subsystem ID */ + 0x00000004, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(0x3, 0x17AA21B5), + AZALIA_PIN_CFG(0x3, 0x04, 0x18560010), + AZALIA_PIN_CFG(0x3, 0x05, 0x18560020), + AZALIA_PIN_CFG(0x3, 0x06, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t410/mainboard.c b/src/mainboard/lenovo/t410/mainboard.c new file mode 100644 index 0000000..23b68fa --- /dev/null +++ b/src/mainboard/lenovo/t410/mainboard.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * Copyright (C) 2013 Vladimir Serbinenko phcoder@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <arch/acpi.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_LFP, 2); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c new file mode 100644 index 0000000..7c796de --- /dev/null +++ b/src/mainboard/lenovo/t410/romstage.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * Copyright (C) 2013 Vladimir Serbinenko phcoder@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <device/pci_ops.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> +#include <northbridge/intel/nehalem/nehalem.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* Enabled, Current table lookup index, OC map */ + { 1, IF1_557, 0 }, + { 1, IF1_55F, 1 }, + { 1, IF1_74B, 3 }, + { 1, IF1_14B, 3 }, + { 1, IF1_14B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_55F, 4 }, + { 1, IF1_55F, 5 }, + { 1, IF1_74B, 7 }, + { 1, IF1_74B, 7 }, + { 1, IF1_557, 7 }, + { 1, IF1_55F, 7 }, +}; + +static void hybrid_graphics_init(void) +{ + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + /* Hide disabled devices */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + else + /* Disable IGD VGA decode, no GTT or GFX stolen */ + pci_write_config16(PCI_DEV(0, 0, 0), D0F0_GGC, 2); + + pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, reg32); +} + +void mainboard_pre_raminit(void) +{ + hybrid_graphics_init(); +} + +void mainboard_get_spd_map(u8 *spd_addrmap) +{ + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x52; +} diff --git a/src/mainboard/lenovo/t410/smihandler.c b/src/mainboard/lenovo/t410/smihandler.c new file mode 100644 index 0000000..91cb0ce --- /dev/null +++ b/src/mainboard/lenovo/t410/smihandler.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/ibexpeak/nvs.h> +#include <southbridge/intel/common/pmutil.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include "dock.h" + +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); + + switch (event) { + case 0x18: + /* Fn-F9 key */ + case 0x27: + /* Power loss */ + case 0x50: + /* Undock Key */ + ec_clr_bit(0x03, 2); + dock_disconnect(); + break; + case 0x37: + case 0x58: + /* Dock Event */ + ec_clr_bit(0x03, 2); + mdelay(250); + dock_connect(); + ec_set_bit(0x03, 2); + /* set dock LED to indicate status */ + ec_write(0x0c, 0x09); + ec_write(0x0c, 0x88); + break; + default: + break; + } +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route H8SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route H8SCI# to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} diff --git a/src/mainboard/lenovo/t410/thermal.h b/src/mainboard/lenovo/t410/thermal.h new file mode 100644 index 0000000..d8c9480 --- /dev/null +++ b/src/mainboard/lenovo/t410/thermal.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Patrick Rudolph siro@das-labor.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t410/vboot-rwa.fmd b/src/mainboard/lenovo/t410/vboot-rwa.fmd new file mode 100644 index 0000000..8f50d33 --- /dev/null +++ b/src/mainboard/lenovo/t410/vboot-rwa.fmd @@ -0,0 +1,31 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_SECTION_A 0x180000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE) 0x40000 + + WP_RO { + RO_VPD(PRESERVE) 0x1000 + RO_SECTION 0x11e000 { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } + } +}