[coreboot-gerrit] Patch merged into coreboot/master: 8a6f7a7 AMD/SB800: Define the GPP PCIe lane distribution

the following patch was just integrated into master:
commit 8a6f7a77f3ab169480b8d22caf1a8d70e3188c62
Author: Dave Frodin 
Date:   Wed Apr 17 18:21:09 2013 -0600

AMD/SB800: Define the GPP PCIe lane distribution

Commit 23023a5 correctly enabled the SB800 GPP PCIe ports but didn't
    distribute the 4 GPP PCIe lanes amongst the enabled PCIe ports.
    This fix was verified by openvoid on a AsRock E350M1 motherboard.

Change-Id: I0116c5f518e0d000be609013446e53da4112f586
    Signed-off-by: Dave Frodin 
    Reviewed-on: http://review.coreboot.org/3104
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich

Build-Tested: build bot (Jenkins) at Thu Apr 18 03:17:59 2013, giving +1
Reviewed-By: Ronald G. Minnich  at Thu Apr 18 18:35:09 2013, giving +2
See http://review.coreboot.org/3104 for details.

-gerrit