Attention is currently required from: Felix Singer, Jamie Ryu, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Raj Astekar. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62772 )
Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock ......................................................................
Patch Set 6:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62772/comment/a20ca332_faeebca0 PS4, Line 16:
Meteor Lake SoC code including this bootblock stage code is based of Alder Lake.
Please mention that in the commit message.
Commit Message:
https://review.coreboot.org/c/coreboot/+/62772/comment/d5caeb1a_917e9e0b PS5, Line 17: Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.corp-partner.google.com Add a TEST= line? If you already have messages, please paste some of them, or at least mention the board you used.
File src/soc/intel/meteorlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/62772/comment/49f3acd0_d7568427 PS5, Line 35: pch_table[] = { : { PCI_DID_INTEL_MTL_ESPI_0, "Meteorlake SOC" }, : { PCI_DID_INTEL_MTL_ESPI_1, "Meteorlake SOC" }, : { PCI_DID_INTEL_MTL_ESPI_2, "Meteorlake SOC" }, : { PCI_DID_INTEL_MTL_ESPI_3, "Meteorlake SOC" }, : { PCI_DID_INTEL_MTL_ESPI_4, "Meteorlake SOC" }, : { PCI_DID_INTEL_MTL_ESPI_5, "Meteorlake SOC" }, : { PCI_DID_INTEL_MTL_ESPI_6, "Meteorlake SOC" }, : { PCI_DID_INTEL_MTL_ESPI_7, "Meteorlake SOC" }, Is the string always the same? If yes, please create a macro or variable?