Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47286 )
Change subject: soc/intel/jasperlake: Enable Intel FIVR RFI settings ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/47286/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47286/2//COMMIT_MSG@9 PS2, Line 9: settings UPD "UPD settings"
https://review.coreboot.org/c/coreboot/+/47286/2/src/soc/intel/jasperlake/ch... File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/47286/2/src/soc/intel/jasperlake/ch... PS2, Line 360: Each Range is translated to an encoded value for FIVR register. 0.5% = 0, 1% : * = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44. These encodings are a little odd, adding an enum or #defines for those would be helpful to people setting this option later
https://review.coreboot.org/c/coreboot/+/47286/2/src/soc/intel/jasperlake/fs... File src/soc/intel/jasperlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/47286/2/src/soc/intel/jasperlake/fs... PS2, Line 220: params->FivrRfiFrequency = config->FivrRfiFrequency;
If FivrSpreadSpectrum default is 0, this should be fine. […]
Is this overriding the FSP default?