Francois Toguo Fotso has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33067 )
Change subject: soc/intel/common: Add SMBIOS type 131 fields ......................................................................
Patch Set 3:
(75 comments)
https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 534: union mkhi_header mkhi_hdr;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 744: }
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 750: void get_mebx_version(mebx_ver *mebx_version )
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 750: void get_mebx_version(mebx_ver *mebx_version )
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 758: }
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 765: pch_capabilities->device_id = pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID);
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 767: }
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 774: if (mkhi_get_fw_version(&version))
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 781: platf_cap->me_major_ver = 0;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 781: platf_cap->me_major_ver = 0;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 781: platf_cap->me_major_ver = 0;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 790: if (mkhi_get_fwcaps(&fw_caps))
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 796: }
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 796: }
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 799: if (mkhi_get_platform_type(&platf_type))
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 801: switch (platf_type.brand)
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 819: }
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 826: if (mkhi_get_fw_fea_state(&fwcaps))
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 845: }
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 856: }
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 861: if (cpu_feature_flag & CPUID_VMX)
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 876: }
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 878: void generate_type131_data(me_smbios_info *me_info, struct smbios_type131 *type131)
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 883: u32 platf_cap[3] = {0,0,0}, nwk_dev_lan[3] = {0,0,0};
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 883: u32 platf_cap[3] = {0,0,0}, nwk_dev_lan[3] = {0,0,0};
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 883: u32 platf_cap[3] = {0,0,0}, nwk_dev_lan[3] = {0,0,0};
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 883: u32 platf_cap[3] = {0,0,0}, nwk_dev_lan[3] = {0,0,0};
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 884: int i,j;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 915: platf_cap[0] |= (pf_cap.me_enabled) ? 1: 0;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 925: for (i=0; i < 3; i++)
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 941: for (j=0; j < 3; j++)
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 942: memcpy(&type131->network_device_lan[j],&nwk_dev_lan[j],4);
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 942: memcpy(&type131->network_device_lan[j],&nwk_dev_lan[j],4);
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 942: memcpy(&type131->network_device_lan[j],&nwk_dev_lan[j],4);
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 952: memcpy(&type131->structure_id, "vPro",4);
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 956: }
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 984: }
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/cse/cse.c... PS1, Line 989: static int smbios_write_type131_info(struct device *dev, int *handle, unsigned long *current)
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https://review.coreboot.org/#/c/33067/2/src/soc/intel/common/block/cse/cse.c File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/#/c/33067/2/src/soc/intel/common/block/cse/cse.c... PS2, Line 793: switch (platf_type.brand) {
switch and case should be at the same indent
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https://review.coreboot.org/#/c/33067/2/src/soc/intel/common/block/cse/cse.c... PS2, Line 860: struct smbios_type131 *type131)
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https://review.coreboot.org/#/c/33067/2/src/soc/intel/common/block/cse/cse.c... PS2, Line 860: struct smbios_type131 *type131)
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https://review.coreboot.org/#/c/33067/2/src/soc/intel/common/block/cse/cse.c... PS2, Line 968: int *handle, unsigned long *current)
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https://review.coreboot.org/#/c/33067/2/src/soc/intel/common/block/cse/cse.c... PS2, Line 968: int *handle, unsigned long *current)
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https://review.coreboot.org/#/c/33067/2/src/soc/intel/common/block/include/i... File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/#/c/33067/2/src/soc/intel/common/block/include/i... PS2, Line 209: } __packed ;
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https://review.coreboot.org/#/c/33067/2/src/soc/intel/common/block/include/i... PS2, Line 224: struct smbios_type131 *type131);
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https://review.coreboot.org/#/c/33067/2/src/soc/intel/common/block/include/i... PS2, Line 224: struct smbios_type131 *type131);
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 58: }__packed cpu_cap;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 66: }__packed pch_cap;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 81: }__packed me_cap;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 104: uint32_t reserved_2 : 1;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 104: uint32_t reserved_2 : 1;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 104: uint32_t reserved_2 : 1;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 108: uint32_t reserve_4 : 1;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 108: uint32_t reserve_4 : 1;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 108: uint32_t reserve_4 : 1;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 111: uint32_t ipv6 : 1;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 111: uint32_t ipv6 : 1;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 111: uint32_t ipv6 : 1;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 113: uint32_t reserve_6 : 1;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 113: uint32_t reserve_6 : 1;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 118: uint32_t reserve_8 : 1;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 118: uint32_t reserve_8 : 1;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 118: uint32_t reserve_8 : 1;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 121: }__packed mefwcaps_sku;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 149: }__packed network_dev;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 159: }__packed bios_cap;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 166: }__packed mebx_ver;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 193: }__packed me_smbios_info;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 208: u8 eos[2];
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 208: u8 eos[2];
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 208: u8 eos[2];
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 209: }__packed ;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 209: }__packed ;
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https://review.coreboot.org/#/c/33067/1/src/soc/intel/common/block/include/i... PS1, Line 223: void generate_type131_data(me_smbios_info *me_info, struct smbios_type131 *type131);
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