Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35383 )
Change subject: drivers/intel/fsp2_0: Allow platform to increase mem overhead ......................................................................
Patch Set 1: Code-Review+1
(2 comments)
Patch Set 1:
(2 comments)
Let me experiment with moving TSEG etc. into cbmem, then I may abandon this.
Got it. I wanted to better understand your thinking/constraints.
https://review.coreboot.org/c/coreboot/+/35383/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35383/1//COMMIT_MSG@13 PS1, Line 13: AMD TSEG
I don't recall now why I put Stoney's TSEG above cbmem_top() -- could be I was trying to mimic an In […]
I was wondering if there were alignment requirements. If so, then this route may indeed be necessary. Depending on how the caching (MTRRs) and protections interact it may be worth not interleaving the regions then.
https://review.coreboot.org/c/coreboot/+/35383/1/src/drivers/intel/fsp2_0/me... File src/drivers/intel/fsp2_0/memory_init.c:
https://review.coreboot.org/c/coreboot/+/35383/1/src/drivers/intel/fsp2_0/me... PS1, Line 44: __weak size_t platform_mem_overhead_size(void) { return 0; }
It doesn't affect cbmem_top(): https://review.coreboot. […]
I see that you are carving out the BERT and TSEG region from the upper end of memory below 4GiB. Presumably platform_mem_overhead_size() returns CONFIG_SMM_TSEG_SIZE + BERT_REGION_MAX_SIZE ?