Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/23594
Change subject: mb/google/poppy/variants/nami: Change WiFi wake pin to GPP_E22 ......................................................................
mb/google/poppy/variants/nami: Change WiFi wake pin to GPP_E22
This change updates the WiFi device wake pin to GPP_E22 from WAKE# (to match the latest schematic changes).
BUG=b:72697650 TEST=Verified: 1. Wake-on-wifi works. 2. Device is able to enter G3 without WAKE# pin causing unwanted wakes from deep S5.
Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d Signed-off-by: Furquan Shaikh furquan@chromium.org --- M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nami/gpio.c 2 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/23594/1
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 348f7de..0149f28 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -5,7 +5,7 @@ register "deep_s3_enable_dc" = "1" register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
# GPE configuration # Note that GPE events called out in ASL code rely on this @@ -291,7 +291,7 @@ device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 on chip drivers/intel/wifi - register "wake" = "GPE0_PCI_EXP" + register "wake" = "GPE0_DW2_22" device pci 00.0 on end end end # PCI Express Port 4 diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index dbee643..e85d948 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -253,8 +253,8 @@ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* E21 : DDPC_CTRLDATA ==> SOC_DP2_CTRL_DATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), - /* E22 : DDPD_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E22), + /* E22 : DDPD_CTRLCLK ==> WLAN_PCIE_WAKE# */ + PAD_CFG_GPI_ACPI_SCI(GPP_E22, NONE, DEEP, INVERT), /* E23 : DDPD_CTRLDATA ==> NC */ PAD_CFG_NC(GPP_E23),