[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Drop Lewis Burg PCIe Root Port IDs

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35983 )

Change subject: soc/intel/common: Drop Lewis Burg PCIe Root Port IDs
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Patch Set 1:
> Patch Set 1:
>
> (I think src/southbridge/intel/ would be a much better place for PCHs)

Me too. Even the lowest-power Skylake chips are two dies on a single package, so not really a SoC...