Attention is currently required from: Nico Huber, Evgeny Zinoviev. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45500 )
Change subject: nb/intel/sandybridge: Improve channel disable logic ......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45500/comment/456dd048_7a62e92d PS5, Line 9: Do not consider the failed channel's SPDs in emergency mode. Also, force
In very weird corner cases, this may fail while it worked before. […]
AIUI, each DIMM would fail to boot without any other DIMMs in the system. Why would a system with two broken DIMMs work?
File src/northbridge/intel/sandybridge/raminit.c:
https://review.coreboot.org/c/coreboot/+/45500/comment/905075ab_c4255692 PS5, Line 348: }
I would much prefer to not write to the cache in emergency mode […]
How would you handle S3 resume, then?