Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8034
-gerrit
commit be00b0c1e88d10980e152dba2531a71509fcf2ba Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Thu Jan 1 14:36:29 2015 +0200
[NOTFORMERGE] google/storm DYNAMIC_CBMEM
Change-Id: I7e13093a038164185a1ab5909e2395e9844e8d50 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/mainboard/google/storm/Kconfig | 2 +- src/mainboard/google/storm/romstage.c | 3 +++ src/soc/qualcomm/ipq806x/Kconfig | 5 +++++ src/soc/qualcomm/ipq806x/Makefile.inc | 2 ++ src/soc/qualcomm/ipq806x/cbmem.c | 25 +++++++++++++++++++++++++ 5 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index a2bf740..1eb8c7e 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -35,6 +35,6 @@ config MAINBOARD_PART_NUMBER
config DRAM_SIZE_MB int - default 2048 + default 512
endif # BOARD_GOOGLE_STORM diff --git a/src/mainboard/google/storm/romstage.c b/src/mainboard/google/storm/romstage.c index cf78e44..10632d8 100644 --- a/src/mainboard/google/storm/romstage.c +++ b/src/mainboard/google/storm/romstage.c @@ -19,12 +19,15 @@
#include <arch/stages.h> #include <cbfs.h> +#include <cbmem.h> #include <console/console.h>
void main(void) { void *entry;
+ cbmem_initialize_empty(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); stage_exit(entry); } diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 09e1c1e..2e21168 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -6,6 +6,7 @@ config SOC_QC_IPQ806X select ARCH_RAMSTAGE_ARMV7 select ARM_LPAE select BOOTBLOCK_CONSOLE + select DYNAMIC_CBMEM select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING
@@ -41,6 +42,10 @@ config BOOTBLOCK_BASE hex "256K bytes left for TZBSP" default 0x40600000
+config SYS_SDRAM_BASE + hex + default 0x40000000 + config STACK_TOP hex default 0x40600000 diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 639b9d9..8212106 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -29,8 +29,10 @@ romstage-y += clock.c romstage-y += gpio.c romstage-y += timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-$(CONFIG_DYNAMIC_CBMEM) += cbmem.c
ramstage-y += cbfs.c +ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c ramstage-y += timer.c diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c new file mode 100644 index 0000000..b175d6a --- /dev/null +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)(CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20)); +}