Martin Roth (gaumless@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10647
-gerrit
commit 1bf6336defad7eea5d83df00b1b6706c72dacd05 Author: Martin Roth gaumless@gmail.com Date: Tue Jun 23 19:59:30 2015 -0600
Move baytrail & fsp_baytrail to the common IFD interface.
- Add the common/firmware subdir to the baytrail & fsp_baytrail makefiles and remove the code it replaces. - Update baytrail & fsp_baytrail Kconfigs to use the common code. - Update the IFD Kconfig help and prompts for the TXE vs ME. - Whittle away at the CBFS_SIZE defaults. All the fsp_baytrail platforms have their own defaults.
Change-Id: I96a9d4acd6578225698dba28d132d203b8fb71a0 Signed-off-by: Martin Roth gaumless@gmail.com --- src/Kconfig | 3 +- src/mainboard/intel/bakersport_fsp/Kconfig | 8 ---- src/mainboard/intel/bayleybay_fsp/Kconfig | 8 ---- src/mainboard/intel/minnowmax/Kconfig | 8 ---- src/mainboard/siemens/mc_tcu3/Kconfig | 4 -- src/soc/intel/baytrail/Kconfig | 58 +-------------------------- src/soc/intel/baytrail/Makefile.inc | 37 +---------------- src/soc/intel/fsp_baytrail/Kconfig | 29 +------------- src/soc/intel/fsp_baytrail/Makefile.inc | 30 +------------- src/southbridge/intel/common/firmware/Kconfig | 14 ++++--- 10 files changed, 13 insertions(+), 186 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig index 94b3508..269f7d2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -342,9 +342,8 @@ config CBFS_SIZE NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || \ - NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL || \ + NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BRASWELL || \ SOC_INTEL_BROADWELL - default 0x200000 if SOC_INTEL_FSP_BAYTRAIL default ROM_SIZE help This is the part of the ROM actually managed by CBFS, located at the diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig index 7f5513a..c382bac 100644 --- a/src/mainboard/intel/bakersport_fsp/Kconfig +++ b/src/mainboard/intel/bakersport_fsp/Kconfig @@ -34,14 +34,6 @@ config MAINBOARD_DIR string default "intel/bayleybay_fsp"
-config INCLUDE_ME - bool - default n - -config LOCK_MANAGEMENT_ENGINE - bool - default n - config MAINBOARD_PART_NUMBER string default "Bakersport CRB (FSP)" diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index 3048126..a5c7605 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -34,14 +34,6 @@ config MAINBOARD_DIR string default "intel/bayleybay_fsp"
-config INCLUDE_ME - bool - default n - -config LOCK_MANAGEMENT_ENGINE - bool - default n - config MAINBOARD_PART_NUMBER string default "Bayley Bay CRB (FSP)" diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 66825c6..636972f 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -33,14 +33,6 @@ config MAINBOARD_DIR string default "intel/minnowmax"
-config INCLUDE_ME - bool - default n - -config LOCK_MANAGEMENT_ENGINE - bool - default n - config MAINBOARD_PART_NUMBER string default "Minnow Max" diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index 6d01e82..9eb396b 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -37,10 +37,6 @@ config MAINBOARD_DIR string default "siemens/mc_tcu3"
-config INCLUDE_ME - bool - default n - config MAINBOARD_PART_NUMBER string default "MC_TCU3 (FSP)" diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 2764efb..5754c15 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -35,6 +35,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC select SOC_INTEL_COMMON + select HAVE_INTEL_FIRMWARE
config BOOTBLOCK_CPU_INIT string @@ -153,63 +154,6 @@ config ENABLE_BUILTIN_COM1 configure the pads and enable it. This serial port can be used for the debug console.
-config HAVE_ME_BIN - bool "Add Intel Management Engine firmware" - default y - help - The Intel processor in the selected system requires a special firmware - for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty/blobs repository. If - not and if you don't have the firmware elsewhere, you can still - build coreboot without it. In this case however, you'll have to make - sure that you don't overwrite your ME firmware on your flash ROM. - -config ME_BIN_PATH - string "Path to management engine firmware" - depends on HAVE_ME_BIN - default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" - -config HAVE_IFD_BIN - bool - default y - -config BUILD_WITH_FAKE_IFD - bool "Build with a fake IFD" - default y if !HAVE_IFD_BIN - help - If you don't have an Intel Firmware Descriptor (ifd.bin) for your - board, you can select this option and coreboot will build without it. - Though, the resulting coreboot.rom will not contain all parts required - to get coreboot running on your board. You can however write only the - BIOS section to your board's flash ROM and keep the other sections - untouched. Unfortunately the current version of flashrom doesn't - support this yet. But there is a patch pending [1]. - - WARNING: Never write a complete coreboot.rom to your flash ROM if it - was built with a fake IFD. It just won't work. - - [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html - -config IFD_BIOS_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_ME_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_PLATFORM_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_BIN_PATH - string "Path to intel firmware descriptor" - depends on !BUILD_WITH_FAKE_IFD - default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" - config HAVE_REFCODE_BLOB depends on ARCH_X86 bool "An external reference code blob should be put into cbfs." diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 78e2da6..7417526 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -9,6 +9,7 @@ subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../southbridge/intel/common/firmware
ramstage-y += memmap.c romstage-y += memmap.c @@ -56,40 +57,6 @@ ramstage-y += placeholders.c
CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
-# Run an intermediate step when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS -INTERMEDIATE:=baytrail_add_me - -ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) -IFD_BIN_PATH := $(objgenerated)/ifdfake.bin -IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ - $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \ - $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%)) -else -IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) -endif - -baytrail_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) -ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) - printf "\n** WARNING **\n" - printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" - printf "Never write a complete coreboot.rom with a fake IFD to your board's\n" - printf "flash ROM! Make sure that you only write valid flash regions.\n\n" - printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" - $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH) -endif - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(IFD_BIN_PATH) \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 -ifeq ($(CONFIG_HAVE_ME_BIN),y) - printf " IFDTOOL me.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - -i ME:$(CONFIG_ME_BIN_PATH) \ - $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif - # If an MRC file is an ELF file determine the entry address and first loadable # section offset in the file. Subtract the offset from the entry address to # determine the final location. @@ -102,6 +69,4 @@ mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS)) mrc.bin-type := mrc
-PHONY += baytrail_add_me - endif diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 95d45da..d51a238 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS + select HAVE_INTEL_FIRMWARE
config SOC_INTEL_FSP_BAYTRAIL_MD bool @@ -94,34 +95,6 @@ config CPU_MICROCODE_CBFS_LOC hex default 0xfff10040
-config INCLUDE_ME - bool "Include the TXE" - default n - help - Build the TXE and descriptor.bin into the ROM image. If you want to use a - descriptor.bin and TXE file from the previous ROM image, you may not want - to build it in here. - -config ME_PATH - string "Path to ME" - depends on INCLUDE_ME - help - The path of the TXE and Descriptor files. - -config LOCK_MANAGEMENT_ENGINE - bool "Lock TXE section" - default n - depends on INCLUDE_ME - help - The Intel Trusted Execution Engine supports preventing write accesses - from the host to the Management Engine section in the firmware - descriptor. If the ME section is locked, it can only be overwritten - with an external SPI flash programmer. You will want this if you - want to increase security of your ROM image once you are sure - that the ME firmware is no longer going to change. - - If unsure, say N. - config ENABLE_BUILTIN_COM1 bool "Enable built-in legacy Serial Port" help diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 92a1fbd..45ea3e4 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -30,6 +30,7 @@ subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../lib/fsp subdirs-y += fsp +subdirs-y += ../../../southbridge/intel/common/firmware
ramstage-y += memmap.c romstage-y += memmap.c @@ -62,33 +63,4 @@ ramstage-y += i2c.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/ CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
-# Run an intermediate step when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS -ifeq ($(CONFIG_INCLUDE_ME),y) -ifneq ($(CONFIG_ME_PATH),) -INTERMEDIATE:=baytrail_add_txe - -baytrail_add_txe: $(obj)/coreboot.pre $(IFDTOOL) - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 - printf " IFDTOOL txe.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - -i ME:$(call strip_quotes,$(CONFIG_ME_PATH))/txe.bin \ - $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) - printf " IFDTOOL Locking Management Engine\n" - $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -else - printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif - -endif -endif - endif diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 71434ac..8ad1fed 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -38,15 +38,17 @@ config IFD_BIN_PATH depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD
config HAVE_ME_BIN - bool "Add Intel Management Engine firmware" + bool "Add Intel ME/TXE firmware" depends on HAVE_IFD_BIN help The Intel processor in the selected system requires a special firmware - for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty/blobs repository. If - not and if you don't have the firmware elsewhere, you can still - build coreboot without it. In this case however, you'll have to make - sure that you don't overwrite your ME firmware on your flash ROM. + for an integrated controller. This might be called the Management + Engine (ME), the Trusted Execution Engine (TXE) or something else + depending on the chip. This firmware might or might not be available + in coreboot's 3rdparty/blobs repository. If it is not and if you don't + have access to the firmware from elsewhere, you can still build + coreboot without it. In this case however, you'll have to make sure + that you don't overwrite your ME/TXE firmware on your flash ROM.
config ME_BIN_PATH string "Path to management engine firmware"