[coreboot-gerrit] Change in coreboot[master]: soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiB

[V Sowmya (Code Review)]

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36032 )

Change subject: soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiB
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Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36032/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36032/4//COMMIT_MSG@9 
PS4, Line 9: The current DCACHE_BSP_STACK_SIZE is set to 128KiB for CML & ICL when FSP uses
           : the same stack provided by coreboot. This patch updates it to 129KiB since the default
           : value of DCACHE_BSP_STACK_SIZE must be the sum of FSP-M stack requirement (128KiB)
           : and CB romstage stack requirement (~1KiB).
> This is exceeding the 75 char linelength however.

Done