[coreboot-gerrit] Change in coreboot[master]: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design

[Shreesh Chhabbi (Code Review)]

Attention is currently required from: Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi.
Shreesh Chhabbi has uploaded a new patch set (#34) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/49766 )

Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
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soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design

This change uses the following information to determine the
appropriate S0ix states to enable as per PDG document: 607872
for TGL UP3 UP Rev2p2 (section 10.13):

1. H/W design - external phy gating, external clk gating, external bypass
2. Devices enabled at runtime - CNVi, ISH

In some cases, it is recommended to use a shallower state for
S0ix even if the higher state can be achieved (e.g. with external
gating not enabled). This recommendation is because the shallower
state is determined to provide better power savings as per the
above document. On tigerlake up3 based platforms, deepest S0ix
substate is S0i3.1.

BUG=b:177821896
TEST=Build coreboot for volteer. Verify that deepest S0ix substate
reached is S0i3.1.

Signed-off-by: Shreesh Chhabbi 
Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 59 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/49766/34