[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update TCSS for SW CM support

[Divya Sasidharan (Code Review)]

Divya Sasidharan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42295 )

Change subject: soc/intel/tigerlake: Update TCSS for SW CM support
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Patch Set 6:
> Patch Set 2:
> > Patch Set 2: Code-Review+1
> >
> > This is needed for SW CM power management support, also disables PCIe tunneling. TBT FW for this is already merged in CL:3107594.
>
> Hi Divya; What will we need to do to re-enable it (from the kernel)? A few folks on our side are looking at PCIe related behaviour (IOMMU enablement, resource allocation etc), so would be good to know if this is something that can be re-enabled via sysfs or kernel command line.
> Based on verification we see no impact with this bit set / clear for PCIe tunneling. But from the comments we got, we understand that clearing this bit should disable the PCIe tunneling permanently. Since we do not want that at this point, in this CL we will keep this bit enabled. Latest patchset already addresses this. For disabling PCIe tunneling we can further discuss here 141545149.