Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 23:
Patch Set 23:
Patch Set 22:
Patch Set 22:
@Meera and Subrata, have you try this on RVP?
Hi Eric, i'll try this today. Can you please rebase this CL?
Done. BTW,it would be better to dump PCIE config in the FSP log to check the CL work or not :) Thank y
Hi Eric, I was able to verify the CL. Please find the PCIe RP Config dump below. ------------------ PCH PCIe RP PreMem Config ------------------ Port[0] RpEnabled= 0 Port[1] RpEnabled= 0 Port[2] RpEnabled= 0 Port[3] RpEnabled= 0 Port[4] RpEnabled= 1 Port[5] RpEnabled= 1 Port[6] RpEnabled= 0 Port[7] RpEnabled= 1 Port[8] RpEnabled= 1 Port[9] RpEnabled= 0 Port[10] RpEnabled= 1 Port[11] RpEnabled= 0 Clock[0] Usage= 40 Clock[0] ClkReq= 0 Clock[1] Usage= 8 Clock[1] ClkReq= 1 Clock[2] Usage= 4 Clock[2] ClkReq= 2 Clock[3] Usage= 41 Clock[3] ClkReq= 3 Clock[4] Usage= 42 Clock[4] ClkReq= 4 Clock[5] Usage= 5 Clock[5] ClkReq= 5 Clock[6] Usage= FF Clock[6] ClkReq= 6 Clock[7] Usage= 80 Clock[7] ClkReq= 6 Clock[8] Usage= FF Clock[8] ClkReq= 8 Clock[9] Usage= FF Clock[9] ClkReq= 9 ClockBuffer= 87