Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46068 )
Change subject: arch/x86/smbios: Populate SMBIOS type 7 with cache information ......................................................................
Patch Set 8: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/46068/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46068/8//COMMIT_MSG@10 PS8, Line 10: Combine L1 Data cache size and : L1 Instruction cache size
Why? […]
In SMBIOS type 4 (processor info), there are handles to cache info in SMBIOS type 7. Right now in SMBIOS type 4, there are 3 handles (eg. L1 D-CACHE and L1 I-CACHE share on handle). In other words, this change aligns with current SMBIOS type 4, and aligns with existing practices in production. I agree that separating L1 D-CACHE and L1 I-CACHE is more accurate. This could be done in next step; otherwise it will cause confusions to users and to apps who make use of SMBIOS type 4 and type 7.
https://review.coreboot.org/c/coreboot/+/46068/8//COMMIT_MSG@11 PS8, Line 11: L1 Instruction cache size, and multiply the cache size of L1 and L2 : by the number of cores
Is there any documentation you followed with these calculations?
For Intel design, each core has its own L1 caches.