[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Add FSP UPDs for minimum assertion widths

[V Sowmya (Code Review)]

Hello build bot (Jenkins), Jamie Chen, Furquan Shaikh, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Krishna P Bhat D, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43791

to look at the new patch set (#6).

Change subject: soc/intel/jasperlake: Add FSP UPDs for minimum assertion widths
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soc/intel/jasperlake: Add FSP UPDs for minimum assertion widths

Add the FSP UPDs for the chipset minimum assertion widths and
Power cycle duration to the chip options which can be configured
per mainboard.

* PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy
* PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy
* PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy
* PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy
* PchPmPwrCycDur: PCH PM Reset Power Cycle Duration
* Check to avoid violating the PCH EDS recommendation for the
  PchPmPwrCycDur setting.

BUG=b:159104150

Change-Id: I042e8e34b7dfda3bc21e5f2e6727cb7692ffc7f7
Signed-off-by: V Sowmya 
---
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/fsp_params.c
2 files changed, 187 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/43791/6