Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45898 )
Change subject: mb/siemens/mc_apl6: Enable eMMC ......................................................................
mb/siemens/mc_apl6: Enable eMMC
Enable eMMC with HS200 mode for mc_apl6 mainboard.
TEST: Linux booted and checked with 'lspci'.
Change-Id: Ib760a1a26a92047e8916979ffb5001bcff0a6e45 Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45898 Reviewed-by: Werner Zeh werner.zeh@siemens.com Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb 1 file changed, 4 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Maxim Polyakov: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index 4aa8bc9..024f2c5 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -14,6 +14,9 @@ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
+ # 0:HS400(Default), 1:HS200, 2:DDR50 + register "emmc_host_max_speed" = "1" + # Enable Vtd feature register "enable_vtd" = "1"
@@ -70,7 +73,7 @@ device pci 19.2 off end # - SPI 2 device pci 1a.0 off end # - PWM device pci 1b.0 on end # - SDCARD - device pci 1c.0 off end # - eMMC + device pci 1c.0 on end # - eMMC device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO device pci 1f.0 on # - LPC