Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45205 )
Change subject: sc7280: Provide initial SoC support ......................................................................
sc7280: Provide initial SoC support
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney mturney@codeaurora.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/45205 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Shelley Chen shchen@google.com --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c 12 files changed, 249 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved
diff --git a/Documentation/soc/qualcomm/index.md b/Documentation/soc/qualcomm/index.md index 5cd7981..d177c0e 100644 --- a/Documentation/soc/qualcomm/index.md +++ b/Documentation/soc/qualcomm/index.md @@ -5,3 +5,4 @@ ## Platforms
- [SC7180 series](sc7180/index.md) +- [SC7280 series](sc7280/index.md) diff --git a/Documentation/soc/qualcomm/sc7280/index.md b/Documentation/soc/qualcomm/sc7280/index.md new file mode 100644 index 0000000..4920805 --- /dev/null +++ b/Documentation/soc/qualcomm/sc7280/index.md @@ -0,0 +1,17 @@ +# Qualcomm SC7280 documentation + +## SOC code + +The SOC folder contains functions for: +* MMU +* CLOCK +* GPIO +* QUPv3 FW (provides a bridge to serial interfaces) +* UART +* SPI-NOR +* AOP FW +* USB + +## Notes about the hardware + +The timer is used from the ARMv8 architecture specific code. diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig new file mode 100644 index 0000000..1bba460 --- /dev/null +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -0,0 +1,29 @@ +config SOC_QUALCOMM_SC7280 + bool + default n + depends on USE_QC_BLOBS + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + select ARM64_USE_ARCH_TIMER + select SOC_QUALCOMM_COMMON + select CACHE_MRC_SETTINGS + select HAS_RECOVERY_MRC_CACHE + +if SOC_QUALCOMM_SC7280 + +config MEMLAYOUT_LD_FILE + string + default "src/soc/qualcomm/sc7280/memlayout.ld" + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + +endif diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc new file mode 100644 index 0000000..15bc039 --- /dev/null +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -0,0 +1,38 @@ +ifeq ($(CONFIG_SOC_QUALCOMM_SC7280),y) + +all-y += ../common/timer.c +all-y += spi.c + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += mmu.c + +################################################################################ +romstage-y += cbmem.c +romstage-y += ../common/qclib.c +romstage-y += ../common/mmu.c +romstage-y += mmu.c + +################################################################################ +ramstage-y += soc.c +ramstage-y += cbmem.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/sc7280/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include + +SC7280_BLOB := $(top)/3rdparty/qc_blobs/sc7180 + +################################################################################ + +QC_SEC_FILE := $(SC7280_BLOB)/qc_sec/qc_sec.mbn +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf + @util/qualcomm/createxbl.py --mbn_version 6 -f $(objcbfs)/bootblock.raw.elf \ + -x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \ + -a 64 -d 64 -c 64 + @printf "\nqgpt.py 4K sector size\n" + @util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \ + $(objcbfs)/bootblock.bin + +endif diff --git a/src/soc/qualcomm/sc7280/bootblock.c b/src/soc/qualcomm/sc7280/bootblock.c new file mode 100644 index 0000000..807bb25 --- /dev/null +++ b/src/soc/qualcomm/sc7280/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/mmu.h> + +void bootblock_soc_init(void) +{ + sc7280_mmu_init(); +} diff --git a/src/soc/qualcomm/sc7280/cbmem.c b/src/soc/qualcomm/sc7280/cbmem.c new file mode 100644 index 0000000..4b9eb37 --- /dev/null +++ b/src/soc/qualcomm/sc7280/cbmem.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> + +void *cbmem_top_chipset(void) +{ + return (void *)((uintptr_t)4 * GiB); +} diff --git a/src/soc/qualcomm/sc7280/include/soc/gpio.h b/src/soc/qualcomm/sc7280/include/soc/gpio.h new file mode 100644 index 0000000..82a0c39 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_GPIO_H_ +#define _SOC_QUALCOMM_SC7280_GPIO_H_ + +#include <types.h> + +typedef struct { + u32 addr; +} gpio_t; + +#endif /* _SOC_QUALCOMM_SC7280_GPIO_H_ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/mmu.h b/src/soc/qualcomm/sc7280/include/soc/mmu.h new file mode 100644 index 0000000..5a2984f --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/mmu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_MMU_H_ +#define _SOC_QUALCOMM_SC7280_MMU_H_ + +void sc7280_mmu_init(void); + +#endif /* _SOC_QUALCOMM_SC7280_MMU_H_ */ diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld new file mode 100644 index 0000000..24b79f9 --- /dev/null +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* SYSTEM_IMEM : 0x14680000 - 0x146AB000 */ +#define SSRAM_START(addr) REGION_START(ssram, addr) +#define SSRAM_END(addr) REGION_END(ssram, addr) + +/* BOOT_IMEM : 0x14800000 - 0x14980000 */ +#define BSRAM_START(addr) REGION_START(bsram, addr) +#define BSRAM_END(addr) REGION_END(bsram, addr) + +/* AOP : 0x0B000000 - 0x0B100000 */ +#define AOPSRAM_START(addr) REGION_START(aopsram, addr) +#define AOPSRAM_END(addr) REGION_END(aopsram, addr) + +SECTIONS +{ + AOPSRAM_START(0x0B000000) + REGION(aop, 0x0B000000, 0x100000, 4096) + AOPSRAM_END(0x0B100000) + + SSRAM_START(0x14680000) + OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + REGION(qcsdi, 0x14699000, 52K, 4K) + SSRAM_END(0x146AB000) + + BSRAM_START(0x14800000) + REGION(pbl_timestamps, 0x14800000, 84K, 4K) + BOOTBLOCK(0x14819000, 40K) + PRERAM_CBFS_CACHE(0x14823000, 70K) + PRERAM_CBMEM_CONSOLE(0x14834800, 32K) + TIMESTAMP(0x1483C800, 1K) + TTB(0x1483D000, 56K) + STACK(0x1484B000, 16K) + VBOOT2_WORK(0x1484F000, 12K) + DMA_COHERENT(0x14853000, 8K) + REGION(ddr_training, 0x14855000, 8K, 4K) + REGION(qclib_serial_log, 0x14857000, 4K, 4K) + REGION(ddr_information, 0x1485B000, 1K, 1K) + FMAP_CACHE(0x1485B400, 2K) + CBFS_MCACHE(0x1485BC00,8K) + REGION(dcb, 0x14875000, 32K, 4K) + REGION(pmic, 0x1487D000, 96K, 4K) + REGION(qclib, 0x14895000, 748K, 4K) + BSRAM_END(0x14950000) + + DRAM_START(0x80000000) + /* Various hardware/software subsystems make use of this area */ + REGION(dram_aop, 0x80800000, 0x040000, 0x1000) + REGION(dram_soc, 0x80900000, 0x200000, 0x1000) + BL31(0x80B00000, 1M) + POSTRAM_CBFS_CACHE(0x9F800000, 16M) + RAMSTAGE(0xA0800000, 16M) +} diff --git a/src/soc/qualcomm/sc7280/mmu.c b/src/soc/qualcomm/sc7280/mmu.c new file mode 100644 index 0000000..9a28578 --- /dev/null +++ b/src/soc/qualcomm/sc7280/mmu.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <symbols.h> +#include <arch/mmu.h> +#include <arch/cache.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols_common.h> + +void sc7280_mmu_init(void) +{ + mmu_init(); + + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); + mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); + mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), + UNCACHED_RAM); + + mmu_enable(); +} diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c new file mode 100644 index 0000000..33d4a69 --- /dev/null +++ b/src/soc/qualcomm/sc7280/soc.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <symbols.h> +#include <device/device.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols_common.h> + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, + ddr_region->size / KiB); + reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB, + REGION_SIZE(dram_soc) / KiB); +} + +static void soc_init(struct device *dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_sc7280_ops = { + CHIP_NAME("SOC Qualcomm SC7280") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/qualcomm/sc7280/spi.c b/src/soc/qualcomm/sc7280/spi.c new file mode 100644 index 0000000..50aa395 --- /dev/null +++ b/src/soc/qualcomm/sc7280/spi.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <spi-generic.h> +#include <spi_flash.h> + +static const struct spi_ctrlr spi_ctrlr; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);