[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake/chip: Unhide P2SB device

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35620 )

Change subject: soc/intel/skylake/chip: Unhide P2SB device
......................................................................

soc/intel/skylake/chip: Unhide P2SB device

APL unhides the P2SB device in coreboot already. Do the same on SKL/KBL.
As the coreboot PCI allocator needs to be able to find the device,
unhide it after FSP-S.

The device is hidden in the SoC finalize function already and not visible
in the OS, as more P2SB device IDs have been added.

Other SoCs aren't updated, because they are too broken.

Fixes "BUG: XXX requests hidden ...." warnings in coreboot log.
Tested on Supermicro X11SSH-TF.

Change-Id: I0d14646098c34d3bf5cd49c35dcfcdce2c57431d
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35620
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
Reviewed-by: Aaron Durbin 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Matt DeVillier 
Reviewed-by: Michael Niewöhner
---
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/finalize.c
2 files changed, 12 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved
  Felix Held: Looks good to me, but someone else must approve
  Furquan Shaikh: Looks good to me, approved
  Matt DeVillier: Looks good to me, approved
  Michael Niewöhner: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 55fedd3..c4f4e50 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -28,6 +28,7 @@
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/mp_init.h>
 #include <intelblocks/xdci.h>
+#include <intelblocks/p2sb.h>
 #include <intelpch/lockdown.h>
 #include <romstage_handoff.h>
 #include <soc/acpi.h>
@@ -175,6 +176,13 @@
    /* Perform silicon specific init. */
    fsp_silicon_init(romstage_handoff_is_resume());

+	/*
+	 * Keep the P2SB device visible so it and the other devices are
+	 * visible in coreboot for driver support and PCI resource allocation.
+	 * There is no UPD setting for this.
+	 */
+	p2sb_unhide();
+
    /* Restore GPIO IRQ polarities back to previous settings. */
    itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);

diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 0d6f737..4cc9c83 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -46,14 +46,6 @@
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS	(1 << 8)

-static void disable_sideband_access(void)
-{
-	p2sb_disable_sideband_access();
-
-	/* hide p2sb device */
-	p2sb_hide();
-}
-
 static void pch_disable_heci(void)
 {
    /* unhide p2sb device */
@@ -63,7 +55,7 @@
    pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
    	PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);

-	disable_sideband_access();
+	p2sb_disable_sideband_access();
 }

static void pch_finalize_script(struct device *dev)
@@ -113,6 +105,9 @@
    /* we should disable Heci1 based on the devicetree policy */
    if (config->HeciEnabled == 0)
    	pch_disable_heci();
+
+	/* Hide p2sb device as the OS must not change BAR0. */
+	p2sb_hide();
 }

static void soc_lockdown(struct device *dev)