[coreboot-gerrit] [S] Change in coreboot[master]: soc/amd/common/block/cpu/Makefile: group build targets by stage

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74009 )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/amd/common/block/cpu/Makefile: group build targets by stage
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soc/amd/common/block/cpu/Makefile: group build targets by stage

Signed-off-by: Felix Held 
Change-Id: Idb6087dc44e76ab63bc6b462c3328c23d83ae018
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74009
Reviewed-by: Fred Reitberger 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/common/block/cpu/Makefile.inc
1 file changed, 17 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Fred Reitberger: Looks good to me, approved

diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc
index 055341e..f198af2 100644
--- a/src/soc/amd/common/block/cpu/Makefile.inc
+++ b/src/soc/amd/common/block/cpu/Makefile.inc
@@ -1,11 +1,12 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 subdirs-y += ./*
-ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE) += update_microcode.c
-romstage-y += cpu.c
-ramstage-y += cpu.c

+romstage-y += cpu.c
+
+ramstage-y += cpu.c
 ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SVI2) += svi2.c
 ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SVI3) += svi3.c
+ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE) += update_microcode.c

ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE),y)
 define add-ucode-as-cbfs