Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45337 )
Change subject: soc/intel/{adl,apl,cnl,ehl,icl,jsl,skl,tgl}: Make use of common reset code block ......................................................................
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Patch Set 5:
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> Patch Set 5: > > @Matt: If you could help me to get this validated quickly on SKL platform > @Werner: Possible to check on APL platform > > I don't have SKL and APL connected remotely in current situation hence i'm working to enable those board for remote test setup. Your help might unblock this.
Hey Subrata. We will have a look at this patch and give it a try on one of our APL-mainboard. I will provide feedback in a few hours. Is a successful boot enough or should I take a closer look to something special?
Hi Subrata, I have tested your patches on mc_apl5. do_global_reset() does not work at all times. During mainboard_init() the HECI device is not available.
Log output: HECI: Global Reset(Type:1) Command BUG: me_read_config32 requests hidden 00:0f.0 PCI: dev is NULL!
In romstage and in mainboard_final (ramstage) the global reset works well.
Thanks a lot for your help. global reset is expected to work post romstage (DRAM initialization been done) somehow we might need to guard the global reset to ensure its not called from verstage or bootblock.
@Furquan, i might need to remove "reset.c" from verstage in https://review.coreboot.org/c/coreboot/+/45336/5/src/soc/intel/common/block/... / do you agree based on Mario's observation that "In romstage and in mainboard_final (ramstage) the global reset works well."
I think it should be okay to drop reset.c from verstage. I don't think we need global reset before romstage anyways. But, it would be good to add a comment to explain the reason in that CL.
Yes Furquan, there are 2 issues
- reset.c can be included in verstage but cse_request_global_reset() as part of cse.c is not included in verstage hence need to drop reset.c from verstage as well.
- global reset via CSE is not working before FSP-M as expected as DID command is not been send hence PMC is one is getting use there. Do we need to document that as well?
Hi Mario,
Can I request you to check latest patch tree to verify once on MC_APL5 platform as you have done previously. Potential fix for this issue is here https://review.coreboot.org/c/coreboot/+/45469/1 (the one you have reported, "PCI: dev is NULL!"). So now you have to pick 4 patches in this tree to see if any issue. Again thanks a lot for your help.