[coreboot-gerrit] Change in coreboot[master]: [WIP]security/intel: Add option to eanble SMM flash access only

[Benjamin Doron (Code Review)]

Attention is currently required from: Patrick Rudolph.
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40830 )

Change subject: [WIP]security/intel: Add option to eanble SMM flash access only
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Patch Set 1:

(1 comment)

Patchset:

PS1:
> Could `fast_spi_init()` in "soc/intel/common/block/smm/smihandler. […]

On the LPC (and therefore, is it perhaps not relevant?), the EISS bit is cleared by `lpc_soc_init` in "src/soc/intel/skylake/lpc.c"

BS_DEV_INIT is after BS_DEV_RESOURCES, where the lock would have been set (but it may not apply to LPC).