[coreboot-gerrit] [XS] Change in coreboot[main]: soc/amd/common/uart: Configure UART PAD

[Naresh Solanki (Code Review)]

Attention is currently required from: Angel Pons, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki.

Hello Angel Pons, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86643?usp=email

to look at the new patch set (#2).

The following approvals got outdated and were removed:
Code-Review+1 by Angel Pons

Change subject: soc/amd/common/uart: Configure UART PAD
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soc/amd/common/uart: Configure UART PAD

On Glinda SoC, UART0 pins like CTS & RTS are also shared with
UART1. During FSP Silicon init, UART1 pins gets reconfigured to UART0
CTS & RTS when initializing it. This leads IOMUX configuration mismatch
for UART1 leading to UART1 non-functional.

To address this, configure UART controller pad when enabling it post
silicon init.

Change-Id: Ie4168e9ea5ecf06e49eace72545d533bf9ab7dcc
Signed-off-by: Naresh Solanki 
---
M src/soc/amd/common/block/uart/uart.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/86643/2