[coreboot-gerrit] Change in coreboot[master]: [WIP]: soc/amd/cezanne: Generate PCI routing table

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Eric Peers, Felix Held.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51556 )

Change subject: [WIP]: soc/amd/cezanne: Generate PCI routing table
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Patch Set 1:

(2 comments)

File src/soc/amd/cezanne/pcie_gpp.c:

https://review.coreboot.org/c/coreboot/+/51556/comment/8f9c7c99_de5985ad 
PS1, Line 88: PPR 55570
Requires fixing - 56569

https://review.coreboot.org/c/coreboot/+/51556/comment/37f3bb35_b6d4974f 
PS1, Line 355: 
Should we also populate the PIRQ data so that amd_pci_util driver can configure PCI_INT_LINE register to each PCI device.