Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41495 )
Change subject: mb/google/deltaur: Remove WLAN PCIE setting ......................................................................
mb/google/deltaur: Remove WLAN PCIE setting
Deltaur uses CNVi WLAN module, this setting is not required.
BUG=none TEST=WiFi is functional in OS.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Idb23e271074c8d1e111c559695d4169af5e0d3cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/41495 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index b2062cb..7350319 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -51,11 +51,6 @@ register "usb3_ports[2]" = "USB3_PORT_EMPTY" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
- # PCIe root port 6 (WLAN), clock 1 - register "PcieRpEnable[5]" = "1" - register "PcieClkSrcUsage[1]" = "5" - register "PcieClkSrcClkReq[1]" = "1" - # PCIe root port 7 (Card Reader), clock 4 register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[4]" = "6" @@ -286,7 +281,7 @@ device pci 1c.2 off end # PCIe Root Port #3 () device pci 1c.3 off end # PCIe Root Port #4 (WWAN) device pci 1c.4 on end # PCIe Root Port #5 (LTE) - device pci 1c.5 on end # PCIe Root Port #6 (WiFi) + device pci 1c.5 off end # PCIe Root Port #6 (WiFi) device pci 1c.6 on end # PCIe Root Port #7 (Card reader) device pci 1c.7 on chip drivers/net