Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Morgan Jang, Shuo Liu, Tim Chu.
Hello Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Morgan Jang, Shuo Liu, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85805?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/xeon_sp/skx: Enable x86_64 ......................................................................
soc/intel/xeon_sp/skx: Enable x86_64
On Xeon Skylake-SP with dual sockets the platforms make use of 46bit of the address space. Most of the PCI BARs reside in high MMIO, not reachable by x86_32 coreboot.
Add support for x86_64 coreboot and confirm that all supported boards are booting without errors. This is done by:
- converting all occurence of VOID * to UINT32 to make sure that FSP UPDs do not change when pointers are 8byte wide. - Drop SetupStructPtr as it's unused within FSP and coreboot
TEST: Booted on ocp/tiogapass to Linux. No errors were observed.
Change-Id: I8adac99e7600a708b596fd74b00669f4cb4e041b Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/ocp/tiogapass/romstage.c M src/soc/intel/xeon_sp/skx/Kconfig M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h 3 files changed, 36 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/85805/2