[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Refactor PCIE port config

[Nico Huber (Code Review)]

Attention is currently required from: Furquan Shaikh, Angel Pons, Michael Niewöhner, EricR Lai.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )

Change subject: soc/intel/alderlake: Refactor PCIE port config
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Patch Set 56:

(1 comment)

File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:

https://review.coreboot.org/c/coreboot/+/48340/comment/b6946ab6_162c20e1 
PS47, Line 22: 	PCIE_RP_CLK_FREE = (1 << 3),
> But, it is still not clear. […]

This looks still unaswered.