Rizwan Qureshi (rizwan.qureshi@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18470
-gerrit
commit 5e45f5303f6931c5e56fd3ac14dc5493ba6b8cf9 Author: Rizwan Qureshi rizwan.qureshi@intel.com Date: Thu Feb 23 15:06:56 2017 +0530
mb/google/poppy: Disbale voltage margining
Voltage margining should be disabled for S0ix to work, disable the voltage margining when SLP_S0# is asserted.
Change-Id: I68d4069563651c65c7b7a9d7fc16f7c12310ac1f Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- src/mainboard/google/poppy/devicetree.cb | 1 + 1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 07cacc0..7f90ad0 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -52,6 +52,7 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" register "SendVrMbxCmd" = "1" # IMVP8 workaround + register "PchPmSlpS0VmEnable" = "0" # Disbale Voltage Margining
register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10"