Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )
Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... PS3, Line 233: TcssAuxOri
My point is why does coreboot not write to this register directly instead of setting the UPD?
Yes. it's doable but takes time as all IOM registers are not available in current EDS. IOM register which assign GPIO is not avaiable. So, can we merge as it is(using FSP UPD) and implement IOM register later when new EDS is available? I'll create partner bug for this for track it. what do you think?
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... PS3, Line 141: memcpy(params->IomTypeCPortPadCfg, config->IomTypeCPortPadCfg, : sizeof(config->IomTypeCPortPadCfg));
Same question as before. […]
Yes. it's doable but takes time as the register info for assign GPIO is not available EDS yet. We already request EDS owner open up the issue. So, can we merge as it is(using FSP UPD) and implement IOM register later when new EDS is available? I'll create partner bug for this for track it. what do you think?