[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/basecode/eop: coreboot driver perform EOP operations

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Arthur Heymans, Felix Singer, Subrata Banik, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 )

Change subject: soc/intel/common/basecode/eop: coreboot driver perform EOP operations
......................................................................

Patch Set 23:

(1 comment)

File src/soc/intel/common/basecode/eop/eop.c:

https://review.coreboot.org/c/coreboot/+/60405/comment/189bd730_51c0b628 
PS23, Line 20: static void do_eop_operations(void *unused)
             : {
             : 	if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) {
             : 		/* Step 1 */
             : 		cse_send_end_of_post();
             : 
             : 		/* Step 2 */
             : 		cse_lock_config();
             : 
             : 		/* Step 3 */
             : 		if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) {
             : 			cse_set_to_d0i3();
             : 			heci1_disable();
             : 		}
             : 	}
             : 
             : 	if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) {
             : 		/* Step 4 */
             : 		heci_set_to_d0i3();
             : 		/* Step 5 */
             : 		pmc_clear_pmcon_sts();
             : 	}
             : }
Thinking out loud even a bit more...........

do these things have to happen here inside their own module?

Aside from `pmc_clear_pmcon_sts` (which seems redundant here to the call in finalize.c for each chipset), these are all fundamentally CSE operations. I wonder if maybe the `.final` callback on the CSE heci1 CSE device is the right place for the other operations? Then we don't require another boot state callback. Right now, I don't believe coreboot is doing anything that would require sending EOP after the device finalize callbacks are happening.