[coreboot-gerrit] Change in coreboot[master]: cpu/amd{family15}: Use common SMM_BASE_MSR

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29065

Change subject: cpu/amd{family15}: Use common SMM_BASE_MSR
......................................................................

cpu/amd{family15}: Use common SMM_BASE_MSR

Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS 
---
M src/cpu/amd/agesa/family15tn/model_15_init.c
M src/cpu/amd/pi/00630F01/model_15_init.c
M src/include/cpu/amd/amdfam15.h
3 files changed, 9 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/29065/1

diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index fdcb9a2..ce0a257 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -15,7 +15,9 @@

#include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
 #include <cpu/x86/smm.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/device.h>
 #include <string.h>
@@ -24,7 +26,6 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
@@ -108,9 +109,9 @@
    	printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);

/* Set SMM base address for this CPU */
-		msr = rdmsr(MSR_SMM_BASE);
+		msr = rdmsr(SMM_BASE_MSR);
    	msr.lo = SMM_BASE - (cpu_idx * 0x400);
-		wrmsr(MSR_SMM_BASE, msr);
+		wrmsr(SMM_BASE_MSR, msr);

/* Enable the SMM memory window */
    	msr = rdmsr(MSR_SMM_MASK);
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
index 0269a1e..803919a 100644
--- a/src/cpu/amd/pi/00630F01/model_15_init.c
+++ b/src/cpu/amd/pi/00630F01/model_15_init.c
@@ -15,8 +15,10 @@

#include <console/console.h>
 #include <cpu/x86/msr.h>
-#include <cpu/x86/smm.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <string.h>
@@ -25,7 +27,6 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>

@@ -105,9 +106,9 @@
    	printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);

/* Set SMM base address for this CPU */
-		msr = rdmsr(MSR_SMM_BASE);
+		msr = rdmsr(SMM_BASE_MSR);
    	msr.lo = SMM_BASE - (cpu_idx * 0x400);
-		wrmsr(MSR_SMM_BASE, msr);
+		wrmsr(SMM_BASE_MSR, msr);

/* Enable the SMM memory window */
    	msr = rdmsr(MSR_SMM_MASK);
diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h
index 271af8a..164ca22 100644
--- a/src/include/cpu/amd/amdfam15.h
+++ b/src/include/cpu/amd/amdfam15.h
@@ -189,7 +189,6 @@
    return MCA_ERRTYPE_UNKNOWN;
 }

-#define MSR_SMM_BASE			0xC0010111
 #define MSR_TSEG_BASE			0xC0010112
 #define MSR_SMM_MASK			0xC0010113
 # define SMM_TSEG_VALID			(1 << 1)