[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake/chip: Unhide P2SB device

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35620 )

Change subject: soc/intel/skylake/chip: Unhide P2SB device
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35620/2/src/soc/intel/skylake/chip_... 
File src/soc/intel/skylake/chip_fsp20.c:

https://review.coreboot.org/c/coreboot/+/35620/2/src/soc/intel/skylake/chip_... 
PS2, Line 184: p2sb_unhide
> now i remember, why we had FSP-S making p2sb hidden from bus
>
> It avoids the BAR0 been modified by PCI BUS enumeration (either by bootloader or by OS). BIOS all hard code the BAR0 as 0xFD000000 so it must not be changed to any other setting.
>
> Please check if PCI enumeration is allocating some other address than above over p2sb bar0 if yes, then we might need to right another p2sb.c to make sure we are doing fixed resource allocation.

https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block/...