Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38942 )
Change subject: treewide: Replace uses of "Nehalem" ......................................................................
treewide: Replace uses of "Nehalem"
The code in coreboot is actually for the Arrandale processors, which are a MCM (Multi-Chip Module) with two different dies:
- Hillel: 32nm Westmere dual-core CPU - Ironlake: 45nm northbridge with integrated graphics
This has nothing to do with the older, single-die Nehalem processors. Therefore, replace the references to Nehalem with the correct names.
Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942 Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M Documentation/mainboard/index.md M src/cpu/intel/common/fsb.c M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_2065x/model_2065x.h M src/drivers/intel/gma/Kconfig M src/include/cpu/intel/em64t101_save_state.h M src/northbridge/intel/ironlake/northbridge.c M src/security/tpm/Kconfig M util/docker/coreboot.org-status/board-status.html/tohtml.sh 9 files changed, 11 insertions(+), 11 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 970f18f..8cb3670 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -75,7 +75,7 @@
- [LT1000](libretrend/lt1000.md)
-### Nehalem series +### Arrandale series
- [T410](lenovo/t410.md)
diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 726ab1c..3dfcd0b 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -48,7 +48,7 @@ *fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; *ratio = (rdmsr(IA32_PERF_STATUS).hi >> 8) & 0x1f; break; - case 0x25: /* Nehalem BCLK fixed at 133MHz */ + case 0x25: /* Arrandale BCLK fixed at 133MHz */ *fsb = 133; *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 1868876..af2606c 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -338,5 +338,5 @@ }
struct chip_operations cpu_intel_model_2065x_ops = { - CHIP_NAME("Intel Nehalem CPU") + CHIP_NAME("Intel Arrandale CPU") }; diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 730ab35..0a07f3c 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -15,7 +15,7 @@ #ifndef _CPU_INTEL_MODEL_2065X_H #define _CPU_INTEL_MODEL_2065X_H
-/* Nehalem bus clock is fixed at 133MHz */ +/* Arrandale bus clock is fixed at 133MHz */ #define IRONLAKE_BCLK 133
#define MSR_CORE_THREAD_COUNT 0x35 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index b66d875..68d4edc 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -39,7 +39,7 @@ To be set by northbridge or mainboard Kconfig. For most platforms, there is no choice, i.e. for i945 and gm45 the SSC reference always differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz - DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and newer, it's + DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Arrandale and newer, it's the same frequency for SSC/non-SSC (120MHz). The only, currently supported platform with a choice seems to be Pineview, where the alternative is 100MHz vs. the default 96MHz. diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h index 7493c85..5d3f9ed 100644 --- a/src/include/cpu/intel/em64t101_save_state.h +++ b/src/include/cpu/intel/em64t101_save_state.h @@ -20,7 +20,7 @@
/* Intel Revision 30101 SMM State-Save Area * The following processor architectures use this: - * - Nehalem + * - Westmere * - SandyBridge * - IvyBridge * - Haswell diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index fe8eed3..91bcc11 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -263,10 +263,10 @@ .ops_pci = &intel_pci_ops, };
-static const struct pci_driver mc_driver_44 __pci_driver = { +static const struct pci_driver mc_driver_ard __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0044, /* Nehalem */ + .device = 0x0044, /* Arrandale DRAM controller */ };
static struct device_operations cpu_bus_ops = { @@ -288,7 +288,7 @@ }
struct chip_operations northbridge_intel_ironlake_ops = { - CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge") + CHIP_NAME("Intel i7 (Arrandale) integrated Northbridge") .enable_dev = enable_dev, .init = ironlake_init, }; diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 95c0bb9..fbe1735 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -99,7 +99,7 @@ Select this to ignore POSTINIT INVALID return codes on TPM startup. This is useful on platforms where a previous stage issued a TPM startup. Examples of use cases are Intel TXT - or VBOOT on the Intel Nehalem northbridge which issues a + or VBOOT on the Intel Arrandale processor, which issues a CPU-only reset during the romstage.
endmenu # Trusted Platform Module (tpm) diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index fa89ae9..2606af4 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -471,7 +471,7 @@ "") case $northbridge in INTEL_IRONLAKE) - cpu_nice="Intel® 1st Gen (Nehalem) Core i3/i5/i7" + cpu_nice="Intel® 1st Gen (Westmere) Core i3/i5/i7" socket_nice="?";; RDC_R8610) cpu_nice="RDC 8610"