[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add macros and SPD information for DDR4

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
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Patch Set 15:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2004
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2003
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2002

Please note: This test is under development and might not be accurate at all!