[coreboot-gerrit] Change in coreboot[master]: amd/common/block/spi: Add EFS SPI configurations to Kconfig

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42567 )

Change subject: amd/common/block/spi: Add EFS SPI configurations to Kconfig
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Patch Set 17:

(2 comments)

https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... 
File src/soc/amd/common/block/spi/Kconfig:

https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... 
PS17, Line 15: 	range 0 7
> To keep it in sync with fch_spi_config_em100_modes: https://source.chromium. […]

em100 supports fast read. the problem with the em100 is mostly in normal read with higher frequencies; fast read adds a dummy byte after the address and before the data transfer which massively relaxes the internal latency requirement

https://review.coreboot.org/c/coreboot/+/42567/17/src/soc/amd/common/block/s... 
PS17, Line 33: 	range 0 5
> I was intending to keep it in sync with the implementation that existed in the spi driver to fch_spi […]

IIRC it generally needs to be at most 33MHz, but for zork devices the maximum frequency was lower due to longer cables. the default of 66MHz will probably break general EM100 support