Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38252 )
Change subject: soc/intel/common/block/cpu/car: Enable caching before FSP-T ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38252/3/src/cpu/x86/16bit/entry16.i... File src/cpu/x86/16bit/entry16.inc:
https://review.coreboot.org/c/coreboot/+/38252/3/src/cpu/x86/16bit/entry16.i... PS3, Line 120: orl $0x01, %eax /* PE = 1 */ that should read MSR 0x13a to see if bootguard is enabled
https://review.coreboot.org/c/coreboot/+/38252/3/src/cpu/x86/Kconfig File src/cpu/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/38252/3/src/cpu/x86/Kconfig@191 PS3, Line 191: cache sets up CAR NEM