Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82728?usp=email )
Change subject: soc/intel/common/block/cse: Prevent HECI commands when flash descriptor override is set ......................................................................
soc/intel/common/block/cse: Prevent HECI commands when flash descriptor override is set
Sending the disable and EOP commands will not work if flash descriptor override is set on Meteor Lake.
Change-Id: I3b5a56229434c9cc326141d48359faa7759541ee Signed-off-by: Jeremy Soller Jeremy@system76.com Signed-off-by: Tim Crawford tcrawford@system76.com --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/include/intelblocks/fast_spi.h 4 files changed, 27 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/82728/1
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d78b8a0..20efd91 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -11,6 +11,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <intelblocks/cse.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/me.h> #include <intelblocks/pmclib.h> #include <intelblocks/post_codes.h> @@ -1310,10 +1311,17 @@
size_t enable_reply_size;
- /* Function Start */ - int send; int result; + + /* Function Start */ + + if (fast_spi_flash_descriptor_override()) { + printk(BIOS_WARNING, "HECI: not setting ME state because " + "flash descriptor override is enabled\n"); + return; + } + /* * Check if the CMOS value "me_state" exists, if it doesn't, then * don't do anything. diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 265fe04..f2701d5 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -4,6 +4,7 @@ #include <bootstate.h> #include <console/console.h> #include <intelblocks/cse.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/pmc_ipc.h> #include <security/vboot/vboot_common.h> #include <soc/intel/common/reset.h> @@ -243,6 +244,11 @@ return; }
+ if (fast_spi_flash_descriptor_override()) { + printk(BIOS_WARNING, "CSE: not sending EOP because flash descriptor override is enabled\n"); + return; + } + if (!eop_sent) { set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); timestamp_add_now(TS_ME_END_OF_POST_START); diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 5382644..91eb1aa 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -483,6 +483,15 @@ write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS); }
+/* Check if flash descriptor override is asserted */ +bool fast_spi_flash_descriptor_override(void) +{ + void *spibar = fast_spi_get_bar(); + uint32_t hsfsts = read32(spibar + SPIBAR_HSFSTS_CTL); + printk(BIOS_DEBUG, "HSFSTS: 0x%X\n", hsfsts); + return !(hsfsts & SPIBAR_HSFSTS_FDOPSS); +} +
/* As there is no official ACPI ID for this controller use the generic PNP ID for now. */ static const char *fast_spi_acpi_hid(const struct device *dev) diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 46b4f48..62195a8 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -111,5 +111,7 @@ * Set FAST_SPIBAR Vendor Component Lock bit. */ void fast_spi_set_vcl(void); +/* Check if flash descriptor override is asserted */ +bool fast_spi_flash_descriptor_override(void);
#endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */