[coreboot-gerrit] Change in coreboot[master]: arch/x86: Add postcar_frame_setup_top_of_dram_usage() API

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34994 )

Change subject: arch/x86: Add postcar_frame_setup_top_of_dram_usage() API
......................................................................

arch/x86: Add postcar_frame_setup_top_of_dram_usage() API

This patch adds new API for intermediate caching top_of_ram
and setting up required MTRR for next stage.

Change-Id: I28d0507083d84e10eef6e1e5482a805067e23847
Signed-off-by: Subrata Banik 
---
M src/arch/x86/include/arch/cpu.h
M src/arch/x86/postcar_loader.c
2 files changed, 40 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/34994/1

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 42c8a97..efee12d 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -332,6 +332,15 @@
 void postcar_frame_common_mtrrs(struct postcar_frame *pcf);

/*
+ * This API performs below operations:
+ * 1. Add variable MTRR covering the Top of DRAM with given MTRR type
+ * 2. Enable intermediate caching of Top of DRAM with given size to speed up
+ *    next stage loading and decompression.
+ */
+void postcar_frame_setup_top_of_dram_usage(struct postcar_frame *pcf,
+				uintptr_t addr, size_t size, int type);
+
+/*
  * Push used MTRR and Max MTRRs on to the stack
  * and return pointer to stack top.
  */
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index 94fde20..f308298 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */

+#include <arch/acpi.h>
 #include <arch/cpu.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -138,6 +139,36 @@
    postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
 }

+/*
+ * Make sure we are enabling intermediate caching to speed up next stage
+ * (postcar/romstage) loading and decompression as we are still in romstage
+ * and CAR tear down will be handled by next stage at its entry.
+ */
+static void enable_top_of_dram_cache(uintptr_t base, size_t size, int type)
+{
+	int mtrr = get_free_var_mtrr();
+
+	if (mtrr == -1)
+		return;
+
+	/* FIXME: setting up type = WB causing hang while loading next stage */
+	set_var_mtrr(mtrr, base, size, type);
+}
+
+void postcar_frame_setup_top_of_dram_usage(struct postcar_frame *pcf,
+				uintptr_t addr, size_t size, int type)
+{
+	/*
+	 * Enable intermediate caching for Top of DRAM to speed up
+	 * next stage loading. No need to enable intermediate caching in S3
+	 * resume path as next stage will be fetched from stage cache
+	 * without any additional locate/decompression logic as normal boot.
+	 */
+	if (!acpi_is_wakeup_s3())
+		enable_top_of_dram_cache(addr, size, type);
+	postcar_frame_add_mtrr(pcf, addr, size, type);
+}
+
 void *postcar_commit_mtrrs(struct postcar_frame *pcf)
 {
    /*